JPH01106944U - - Google Patents
Info
- Publication number
- JPH01106944U JPH01106944U JP225488U JP225488U JPH01106944U JP H01106944 U JPH01106944 U JP H01106944U JP 225488 U JP225488 U JP 225488U JP 225488 U JP225488 U JP 225488U JP H01106944 U JPH01106944 U JP H01106944U
- Authority
- JP
- Japan
- Prior art keywords
- cache
- circuit
- cpu
- instruction
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は本考案に係るＣＰＵ内部キヤツシユ・
モニタ回路の一実施例を示す要部構成図、第２図
は動作を説明するためのタイムチヤート、第３図
は本考案の一具体例を示す構成図、第４図は従来
の一般的なインサーキツト・エミユレータの一例
を示す概念的構成図である。
１０……命令追跡回路、２０……キヤツシユ・
タイミング・モニタ回路、３０……キヤツシユ・
サンプル回路。
Figure 1 shows the CPU internal cache according to the present invention.
FIG. 2 is a time chart for explaining the operation, FIG. 3 is a configuration diagram showing a specific example of the present invention, and FIG. 4 is a conventional general configuration diagram. 1 is a conceptual configuration diagram showing an example of an in-circuit emulator. 10...Instruction tracking circuit, 20...Cash
Timing monitor circuit, 30...cash
Sample circuit.
Claims (1)
はキヤツシユ内容のモニタあるいはキヤツシユを
アクセスしたバスサイクルのトレースが不可能な
ＣＰＵを対象とするものであつて、 キヤツシユをヒツトする命令の発生タイミング
および命令タイプを検出する命令追跡回路と、 前記命令追跡回路での前記検出の後数バスサイ
クル内に前記ＣＰＵから出力されるバスクロツク
信号が３バスサイクル間アクテイブになるキヤツ
シユ・アクセス・サイクルをモニタし、そのタイ
ミングのデータバスをサンプルするための信号お
よびその他の必要な信号を生成するキヤツシユ・
タイミング・モニタ回路と、 インサーキツト・エミユレータ本体側からその
内容を読み出すことができ、必要に応じて前記キ
ヤツシユの内容を読み取つて記憶すると共に、リ
アルタイムでアクセスされたキヤツシユのタイプ
を判断してセレクトできるポインタを備えたキヤ
ツシユ・サンプル回路 とを具備したことを特徴とするＣＰＵ内部キヤ
ツシユ・モニタ回路。[Scope of Claim for Utility Model Registration] The object is a CPU that has a cache inside the CPU, and it is normally impossible to monitor the contents of the cache or trace the bus cycle that accessed the cache from the outside, and that does not hit the cache. an instruction tracking circuit for detecting instruction generation timing and instruction type; and a cache access circuit in which a bus clock signal output from the CPU is active for three bus cycles within several bus cycles after the instruction detection by the instruction tracking circuit. The cache monitors the cycle and generates the signals to sample the data bus for that timing and other necessary signals.
A timing monitor circuit and a pointer that can read the contents of the cache from the incircuit emulator main body side, read and store the contents of the cache as necessary, and determine and select the type of cache accessed in real time. A cache monitor circuit inside a CPU, comprising: a cache sample circuit having the following features:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP225488U JPH01106944U (en) | 1988-01-12 | 1988-01-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP225488U JPH01106944U (en) | 1988-01-12 | 1988-01-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01106944U true JPH01106944U (en) | 1989-07-19 |
Family
ID=31202863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP225488U Pending JPH01106944U (en) | 1988-01-12 | 1988-01-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01106944U (en) |
-
1988
- 1988-01-12 JP JP225488U patent/JPH01106944U/ja active Pending
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