JPH0289415A - Double frequency signal generation circuit - Google Patents

Abstract

PURPOSE:To generate a waveform of a pulse having a half of the duty cycle and a double frequency by making up of a double frequency generating circuit with a clock generator, a counter, a count-back counter, a differentiator detecting the leading or trailing of the waveform and an FF. CONSTITUTION:Data of a counter 2 except the low-order 1 bit is moved to a count-back counter 3 by an output of a differentiator 6, and the data of the counter 2 except the low-=order 2-bit is moved to a count-back counter 4 to reset the counter 2 and to set the count-back counter 5. Then the count of a clock signal of a clock generator 1 is started by the counter 2 and the count-back of the count-back counters 3,4 is started and the count-back counter 5 is reset when the counter 4 is cleared and the data of the counter 3 is shifted toward the high-order by one bit and moved to the counter. The counter 5 starts decrementing to set an FF 7 when the counter 3 is cleared. Moreover, when the counter 3 is cleared, the FF 7 is reset to produce a pulse train with a double frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to converting a repetitive pulse train of an arbitrary duty cycle into a pulse train of twice the frequency at a duty cycle of 1/2.

Conventional technology In the conventional example, a trigger generation circuit generates a pulse train by 1/4.
By delaying the duty cycle 1 by the period
/2, it is possible to create a pulse train with twice the frequency.

Problems to be Solved by the Invention However, with the above-mentioned conventional configuration, it is difficult to accurately achieve a delay of 1/4 period.

Further, in cases other than pulse trains with a duty cycle of 1/2, it was not possible to create a pulse train with twice the frequency at a duty cycle of 1/2.

Means for Solving the Problems To achieve this object, the frequency doubler generation circuit of the present invention includes a clock generator, a counter driven by this clock, and a countercounter, which detects the rising or falling edge of a waveform. It consists of a differentiator, a counter, and a flip-flop driven by an inverse counter.

Operation: With this configuration, a pulse train of an arbitrary duty cycle can be counted with clock pulses of a cycle sufficiently shorter than this cycle, and a waveform with twice the frequency can be generated at a duty cycle of 1/2.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. In FIG. 1, 1 is a clock generator, 2 is a counter driven by a signal from clock generator 1, and 3 is a counter driven by a signal from clock generator 1.
, 4.5 are inverse counters driven by the signal of the clock generator 1, 6 is a differentiator for detecting the rising or falling edge of the signal, and 7 is a counter driven by the counter 2 and the inverse counters 3, 4.5. It is a driven flip-flop. First, the output of the differentiator 6 is used to remove the lower 1 bit from the counter 2 data and transfer it to the inverse counter 3, and then remove the lower 2 bits from the counter 2 data and transfer it to the inverse counter 4, reset the counter 2, and transfer the data from the counter 2 to the inverse counter 4. Set step 5.

After that, the counter 2 starts counting the clock signal of the clock generator 1, and the counters 3 and 4 start subtracting, and when the counter 4 becomes clear, the flip-flop 5 is reset, and the counters 3 and 4 start subtracting. 3
The data is shifted to the upper bit by one bit and transferred to the inverse calculation counter 5.

The backward counter 5 starts subtraction, and when the backward counter 3 becomes clear, the flip-flop 7 is set. Further, when the reverse counter 5 becomes clear, the flip-flop 7 is reset. As above,
1/2 times the data of counter 2 is sent to inverse counter 3, and 1
/4 times is transferred to inverse counter 4, and flip-flop 7
At the time when is set, the output of the flip-flop 7 becomes high level, after which the inverse counters 3 and 4 subtract, the inverse counter 4 becomes clear state, and when the flip-flop 7 is reset, the output of the flip-flop 7 becomes high level. The output of becomes low level, and the inverse calculation counter 5 starts subtraction. Further, when the reverse counter 3 goes into the clear state and the flip-flop 7 is set, the output of the flip-flop 7 becomes high level, the reverse counter 5 subtracts, the counter 5 goes into the clear state, and the flip-flop 7 When reset, the output of the flip-flop 7 is at a low level, making it possible to create a pulse train with twice the frequency and a duty cycle of 1/2.

Effects of the Invention As described above, according to the present invention, the clock generator 1, the counter 2, the inverse counter 3.4.5, the delay circuit 6,
By providing the flip-flop 7, a pulse of twice the frequency can be generated with a duty cycle of 1/2.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention. 1... Clock generator, 2... Counter, 3... Counter counter, 4... Counter counter, 5... Counter counter, 6...
・Differentiator, 7...Flip-flop.

Claims (1)

[Claims] a clock generator, a counter driven by the clock, a first inverse counter, a second inverse counter, a third inverse counter, a differentiator for detecting a rising or falling edge of a signal; a flip-flop driven by first to third inverse counting counters; the output of the differentiator is used to transfer the data of the counter except for the lower 1 bit to the first inverse counting counter; remove the lower two bits and transfer them to the second inverse counter, reset the counter, set the flip-flop, start clock counting of the clock generator with the counter, and When subtraction is started with the second backward counting counter and the second backward counting counter is in a clear state,
resetting the flip-flop and shifting the data of the first inverse counter by one bit;
and starts subtraction in the third counter, and when the first counter becomes clear, sets the flip-flop so that the third counter counter starts subtracting. A double frequency signal generation circuit, wherein the flip-flop is reset when the flip-flop is in a clear state.