JPH0298644U - - Google Patents
Info
- Publication number
- JPH0298644U JPH0298644U JP1989007336U JP733689U JPH0298644U JP H0298644 U JPH0298644 U JP H0298644U JP 1989007336 U JP1989007336 U JP 1989007336U JP 733689 U JP733689 U JP 733689U JP H0298644 U JPH0298644 U JP H0298644U
- Authority
- JP
- Japan
- Prior art keywords
- cavity
- center
- semiconductor package
- forming
- periphery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Die Bonding (AREA)
Description
第１図Ａ，Ｂは本考案に係る半導体パツケージ
の第１の実施例を示す断面図と平面図、第２図Ａ
，Ｂは本考案による第２の実施例を示す断面図と
平面図、第３図Ａ，Ｂは従来例の断面図と平面図
である。 １，１１……キヤビテイ、１ａ……第２のキヤ
ビテイ、２，１２……ステツチ、３，１３……外
部導出ピン、４，１４……半導体パツケージ、５
，１５……半導体チツプ、６，１６……ボンデイ
ングワイヤ。
の第１の実施例を示す断面図と平面図、第２図Ａ
，Ｂは本考案による第２の実施例を示す断面図と
平面図、第３図Ａ，Ｂは従来例の断面図と平面図
である。 １，１１……キヤビテイ、１ａ……第２のキヤ
ビテイ、２，１２……ステツチ、３，１３……外
部導出ピン、４，１４……半導体パツケージ、５
，１５……半導体チツプ、６，１６……ボンデイ
ングワイヤ。
Claims (1)
- 半導体パツケージにおいて、キヤビテイのセン
タ部を周辺部より一段低い階段状に形成するか或
いはキヤビテイの４辺をセンタに向かつて傾斜さ
せて形成することにより、キヤビテイ面の周辺と
センタで高さが違うことを特徴とする半導体パツ
ケージ。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989007336U JPH0298644U (ja) | 1989-01-24 | 1989-01-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989007336U JPH0298644U (ja) | 1989-01-24 | 1989-01-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0298644U true JPH0298644U (ja) | 1990-08-06 |
Family
ID=31212264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989007336U Pending JPH0298644U (ja) | 1989-01-24 | 1989-01-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0298644U (ja) |
-
1989
- 1989-01-24 JP JP1989007336U patent/JPH0298644U/ja active Pending