JPH0318227A - High-voltage pulse noise absorbing element - Google Patents
High-voltage pulse noise absorbing elementInfo
- Publication number
- JPH0318227A JPH0318227A JP15345789A JP15345789A JPH0318227A JP H0318227 A JPH0318227 A JP H0318227A JP 15345789 A JP15345789 A JP 15345789A JP 15345789 A JP15345789 A JP 15345789A JP H0318227 A JPH0318227 A JP H0318227A
- Authority
- JP
- Japan
- Prior art keywords
- concentration diffusion
- diffusion layer
- low
- concentration
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 208000035795 Hypocalcemic vitamin D-dependent rickets Diseases 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 208000033584 type 1 vitamin D-dependent rickets Diseases 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、MOS型半導体集積回路の、オープンドレイ
ン型MOSFETの高耐圧出力素子に釦いて、外部の負
荷回路の結合容量によう誘起されて発生した高電圧パル
ス・ノイズを吸収する素子に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to a high breakdown voltage output element of an open drain MOSFET of a MOS semiconductor integrated circuit, which is induced by the coupling capacitance of an external load circuit. This invention relates to an element that absorbs high voltage pulse noise.
従来の技術
第3図に従来用いられているオープンドレイン型MOS
FETの高剛圧出力素子の一部である拡散抵抗素子を示
した。導電型半導体基板咬たはその中に形成したウェル
拡散層9と反対の導電型の低濃度拡散層1oを形成し、
その両端部にコンタクトをとるために、基板咬たはウヱ
ノレ9と反対の導電型の高濃度拡散層11 .12が付
設されておりそれぞれ高耐圧出力端子vOUT、固定電
位である高電圧電源端子■PP に接続されている。第
4図はその等価回路を示したものである。Conventional technology Figure 3 shows an open drain type MOS conventionally used.
A diffusion resistance element, which is a part of a high-rigidity output element of an FET, is shown. Forming a low concentration diffusion layer 1o of the conductivity type opposite to the well diffusion layer 9 formed on or in the conductivity type semiconductor substrate,
In order to make contact with both ends of the substrate, a high concentration diffusion layer 11. 12 are attached, and are respectively connected to a high voltage output terminal vOUT and a high voltage power supply terminal ■PP having a fixed potential. FIG. 4 shows the equivalent circuit.
発明が解決しようとする課題
3ベー,
第3図において、vOUT端子11に出力される電圧は
vDDから■PPの電圧となる。ここで■DDは集積回
路の電源電圧であシ、vPP は高電圧電源の電圧値で
ある。vOUT端子11は外部装置、たとえば螢光表示
管などの配線基板上の浮遊容量の影響によシ隣接する別
の■OUT端子の矩形波から寄生的に発生するパルス・
ノイズの影響を受ける。例えばVDD=5V,VPP=
−30Vで、”OUT端子11はvPP電位に固定され
ている場合、別の■OUT 端子が5■から−30v4
で動作し矩形波を発生するとVOUT端子11には理論
的には■○UT = − 6 5 V ’Jでの電圧が
パルス的に発生することになり、低濃度拡散層1oの耐
圧は〜2 .X l V p p−Vr,Dl二70■
程度必要となる。この耐圧は使用している高電圧電源の
電圧値の2倍以上となっている。微細化が進むMOS
LSIの製造技術では限界近くとなり、製造技術で解
決するのは困難となりつつある。素子耐圧が
〜2×1■PP−vDD1以下の素子が使われた場合に
はパルス・ノイズの影響による素子破壊,特性本発明は
高耐圧出力端子でパルス・ノイズの発生を防ぐためには
、高耐圧出力端子で発生する電位の絶対値が高電圧電源
電位の絶対値より大きくなった場合に、高耐圧端子と高
電圧電源端子間を導通させる素子,高電圧パルスノイズ
吸収素子を従来の拡散抵抗素子と並列に設置するもので
ある。Problem to be Solved by the Invention 3. In FIG. 3, the voltage output to the vOUT terminal 11 changes from vDD to ■PP. Here, DD is the power supply voltage of the integrated circuit, and vPP is the voltage value of the high voltage power supply. The vOUT terminal 11 receives pulses and pulses parasitically generated from the rectangular wave of another adjacent OUT terminal due to the influence of stray capacitance on the wiring board of an external device such as a fluorescent display tube.
Affected by noise. For example, VDD=5V, VPP=
-30V, if the OUT terminal 11 is fixed at vPP potential, another OUT terminal 5 to -30v4
When it operates and generates a rectangular wave, theoretically a voltage of ■○UT = - 6 5 V 'J will be generated in a pulse form at the VOUT terminal 11, and the withstand voltage of the low concentration diffusion layer 1o is ~2 .. X l V p p-Vr, Dl270■
degree is required. This withstand voltage is more than twice the voltage value of the high voltage power supply used. MOS is becoming increasingly miniaturized
LSI manufacturing technology is nearing its limits, and it is becoming difficult to solve the problem with manufacturing technology. If an element with an element withstand voltage of ~2×1■PP-vDD1 or less is used, the element will be destroyed due to the influence of pulse noise.The characteristics of this invention When the absolute value of the potential generated at the withstand voltage output terminal becomes larger than the absolute value of the high voltage power supply potential, the high voltage pulse noise absorbing element, which is an element that connects the high voltage terminal and the high voltage power supply terminal, is replaced with a conventional diffused resistor. It is installed in parallel with the element.
作 用
本発明による高電圧パルス・ノイズ吸収素子は高耐圧出
力端子と高電圧電源端子の二つの端子をソースおよびド
レインとし、ゲートは高耐圧出力端子と接続されている
。ソース、釦よびドレインは導電型半導体基板1たはそ
の中に形成したウェルに対してIVPP−VDD I以
上の耐圧を有する構造とする.従来の拡散抵抗素子の抵
抗をR,本発明による高電圧パルス・ノイズ吸収素子の
抵抗をr,閾値電圧を■Iとすると、
(1) ■DD〉■OUT〉vPP+v工の場合Bvd
〈■PP−vDD
5.,−,
r ))R ( R=1ooxΩ)(2) vOU
T<vPP+vIの場合Bvd二 〇
r (( R
となる。ここでBvd は高電圧パルス・ノイズ吸収素
子のソース・ドレイン間の耐圧を示し、ンス・ドレイン
はP型拡散層の場合とした。Function The high voltage pulse noise absorbing element according to the present invention has two terminals, a high voltage output terminal and a high voltage power supply terminal, as a source and a drain, and a gate is connected to the high voltage output terminal. The source, button, and drain have a structure that has a breakdown voltage of IVPP-VDDI or more with respect to the conductive semiconductor substrate 1 or the well formed therein. Assuming that the resistance of the conventional diffused resistance element is R, the resistance of the high voltage pulse noise absorbing element according to the present invention is r, and the threshold voltage is ■I, (1) Bvd in the case of ■DD>■OUT>vPP+v
<■PP-vDD 5. , −, r )) R ( R = 1ooxΩ) (2) vOU
When T<vPP+vI, Bvd20r ((R). Here, Bvd indicates the withstand voltage between the source and drain of the high voltage pulse noise absorbing element, and the source and drain are assumed to be P-type diffusion layers.
(1)は高耐圧出力端子が通常の動作状態の場合であシ
ハルス・ノイズ吸収素子のソース・ドレイン間は非導通
となる。(1) is a case where the high voltage output terminal is in a normal operating state, and there is no conduction between the source and drain of the Sihals noise absorbing element.
(2)は高耐圧出力端子に■PP以下のパルス・ノイズ
が発生した場合であシバルス・ノイズ吸収素子は導通状
態となる。(2) is a case where a pulse noise of less than ■PP occurs at the high voltage output terminal, and the Sibar noise absorbing element becomes conductive.
実施例 第1図は本発明による実施例を示したものである。Example FIG. 1 shows an embodiment according to the present invention.
導電型半導体基板1たはその中に形成したウェル拡散層
1と反対の導電型の2つの低掛度拡散層領域2,3を距
離Lだけ離して設置し、その中間の領域8の基板捷たは
ウェノレ表面濃度をイオン注入6、,7
などによりある特定の濃度に制御した後、分離用厚膜7
を形成し分離用厚膜が形戊されていない前記2つの低濃
度拡散層領域2,3の中心部には2,3と同一の導電型
の高濃度拡散層4,5を低濃度拡散層領域2,3からは
み出さないように形成する。低濃度拡散層2,3の形成
は高濃度拡散層4,5の形成の後でも構わない。高濃度
拡散層4,5の中間位置の厚膜上にゲート電極を設け、
ソース側の電極、vOUT端子(高濃度拡散層4)と接
続する。Two low-intensity diffusion layer regions 2 and 3 of the conductivity type opposite to the conductivity type semiconductor substrate 1 or the well diffusion layer 1 formed therein are set apart by a distance L, and the substrate is separated in the region 8 in the middle thereof. After controlling the concentration on the surface of the liquid to a certain concentration by ion implantation 6, 7, etc., the thick separation film 7 is
In the center of the two low concentration diffusion layer regions 2 and 3 where a thick separation film is not formed, a high concentration diffusion layer 4 and 5 of the same conductivity type as 2 and 3 is formed as a low concentration diffusion layer. It is formed so as not to protrude from areas 2 and 3. The low concentration diffusion layers 2 and 3 may be formed after the high concentration diffusion layers 4 and 5 are formed. A gate electrode is provided on the thick film at an intermediate position between the high concentration diffusion layers 4 and 5,
Connected to the source side electrode and vOUT terminal (high concentration diffusion layer 4).
ドレイン側の電極は■PP 端子(高濃度拡散層6)と
する。The electrode on the drain side is a PP terminal (high concentration diffusion layer 6).
本素子が動作する閾値電圧の制御は低濃度拡散領域2,
3の距離Lと、8の領域の表面濃度によって行なう。The threshold voltage at which this device operates is controlled by the low concentration diffusion region 2,
This is done using the distance L of 3 and the surface concentration of the area of 8.
第2図は本発明による素子を従来の拡散抵抗素子に並列
に付加した場合を等価回路で示したものである。FIG. 2 shows an equivalent circuit in which the element according to the present invention is added in parallel to a conventional diffused resistance element.
発明の効果
本発明による素子を用−ることにより、オープンドレイ
ン型MOSFETの高耐圧出力素子にかい了、
て外部の負荷回路からの結合容量による高電圧のパルス
・ノイズを消去するこどが可能となり、高耐圧出力素子
特性の安定化,信頼性の向上が出来、MOS LSI
の製造技術上の制約を軽減できる。Effects of the Invention By using the element according to the present invention, it is possible to eliminate high voltage pulse noise due to coupling capacitance from an external load circuit by passing through the high voltage output element of an open drain MOSFET. As a result, it is possible to stabilize the characteristics of high-voltage output elements and improve reliability, making it possible to improve MOS LSI
can reduce manufacturing technology constraints.
第1図は本発明によるパルス・ノイズ吸収素子を示した
断面図、第2図は等価回路による本発明の利用方法を示
した回路図、第3図は従来例の拡散抵抗を示した断面図
、第4図は等価回路による従来例を示した回路図である
。
1・・・・・導電型半導体基板1たは、その中に形成し
たウェノレ拡散層、2,3・・・・・1と反対の導電型
の低濃度拡散層、4,5・・・・・1と反対の導電型の
高濃度拡散層、6・・・・・ゲート電極、ア・・・・・
厚い酸化膜、8・・・・・・低濃度拡散層2,30間の
領域、9・・・・・・導電型半導体基板筐たはその中に
形成したウェル拡散層、10・・・・・・9と反対の導
電型の低濃度拡散層、11.12・・・・・・9と反対
の導電型の高濃度散層層、11・・・・・■OUT端子
、12・・・・・・■PP端子、13・・・・・・厚い
酸化膜、L・・・・・・低濃度拡散層2,3の間の距離
、r・・・・・本発明による素子の抵抗、R・・・・・
従来例の拡散抵抗の抵抗、■OUT・・・・・高耐圧出
力端子電圧,端子名、■PP・・・・・高電圧電源端子
電圧,端子名。Fig. 1 is a cross-sectional view showing a pulse noise absorbing element according to the present invention, Fig. 2 is a circuit diagram showing a method of utilizing the present invention using an equivalent circuit, and Fig. 3 is a cross-sectional view showing a conventional diffused resistor. , FIG. 4 is a circuit diagram showing a conventional example using an equivalent circuit. 1... Conductivity type semiconductor substrate 1 or a weno diffusion layer formed therein, 2, 3... Low concentration diffusion layer of the opposite conductivity type to 1, 4, 5...・High concentration diffusion layer of conductivity type opposite to 1, 6...gate electrode, a...
Thick oxide film, 8...A region between the low concentration diffusion layers 2 and 30, 9...A conductive semiconductor substrate casing or a well diffusion layer formed therein, 10... ...Low concentration diffused layer of conductivity type opposite to 9, 11.12...High concentration diffusion layer of conductivity type opposite to 9, 11...■OUT terminal, 12... ...■PP terminal, 13...Thick oxide film, L...Distance between low concentration diffusion layers 2 and 3, r...Resistance of the element according to the present invention, R...
Resistance of conventional diffused resistor, ■OUT...High voltage output terminal voltage, terminal name, ■PP...High voltage power supply terminal voltage, terminal name.
Claims (1)
散層と反対の導電型の2つの低濃度拡散層をある特定の
距離だけ離して設置し、前記低濃度拡散層の中間領域の
基板表面濃度をある特定の濃度に設定した後に、前記低
濃度拡散層の表面領域の中心部以外に厚い酸化膜を成長
させ、厚い酸化膜が形成されていない低濃度拡散層の表
面領域における中心部以外には、この低濃度拡散層と同
一の導電型の高濃度のソース・ドレイン拡散層を低濃度
拡散層の領域からはさみ出さないようにそれぞれ形成し
、高濃度のソース・ドレイン拡散層の中間の位置にある
厚い酸化膜上にはゲート電極を設置し、高濃度のソース
・ドレイン拡散層とゲート電極を接続させて、高耐圧出
力端子とし、他方の高濃度のソース・ドレイン拡散層は
固定電位の高電圧電源端子とする構造を有することを特
徴とする高電圧パルス・ノイズ吸収素子。A conductive type semiconductor substrate or two low concentration diffusion layers of the opposite conductivity type to the well diffusion layer formed therein are installed at a certain distance apart, and the substrate surface concentration in the intermediate region of the low concentration diffusion layers is set. After setting a certain concentration, a thick oxide film is grown in areas other than the center of the surface area of the low concentration diffusion layer, and a thick oxide film is grown in areas other than the center of the surface area of the low concentration diffusion layer where a thick oxide film is not formed. , high-concentration source/drain diffusion layers of the same conductivity type as this low-concentration diffusion layer are formed so as not to extend from the region of the low-concentration diffusion layer, and are placed at intermediate positions between the high-concentration source/drain diffusion layers. A gate electrode is installed on one thick oxide film, and the gate electrode is connected to a high concentration source/drain diffusion layer to form a high voltage output terminal. A high voltage pulse noise absorbing element characterized by having a structure as a voltage power supply terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15345789A JPH0318227A (en) | 1989-06-15 | 1989-06-15 | High-voltage pulse noise absorbing element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15345789A JPH0318227A (en) | 1989-06-15 | 1989-06-15 | High-voltage pulse noise absorbing element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0318227A true JPH0318227A (en) | 1991-01-25 |
Family
ID=15562978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15345789A Pending JPH0318227A (en) | 1989-06-15 | 1989-06-15 | High-voltage pulse noise absorbing element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0318227A (en) |
-
1989
- 1989-06-15 JP JP15345789A patent/JPH0318227A/en active Pending
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