JPH0323896U - - Google Patents

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Publication number
JPH0323896U
JPH0323896U JP8376789U JP8376789U JPH0323896U JP H0323896 U JPH0323896 U JP H0323896U JP 8376789 U JP8376789 U JP 8376789U JP 8376789 U JP8376789 U JP 8376789U JP H0323896 U JPH0323896 U JP H0323896U
Authority
JP
Japan
Prior art keywords
word line
memory cell
limiter circuit
diodes
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8376789U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8376789U priority Critical patent/JPH0323896U/ja
Publication of JPH0323896U publication Critical patent/JPH0323896U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】
第1図は本考案によるワード線リミツタ回路を
説明する回路図、第2図は本考案および従来のリ
ミツト電位特性を説明する特性図、第3図は従来
のワード線リミツタ回路を説明する回路図である
。 1……ワード線昇圧回路、2……メモリセル、
3……ワード線リミツタ回路、4……MOSダイ
オードである。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 1トランジスタ、1キヤパシタのメモリセ
    ルと前記メモリセルに接続されたワード線と前記
    ワード線の電位を書き込み時に昇圧するワード線
    昇圧回路とを具備し、前記ワード線昇圧回路と前
    記メモリセル間にゲートドレイン間を接続したM
    OSダイオードを複数個接続したことを特徴とす
    るワード線リミツタ回路。 (2) 前記MOSダイオードの個数を電源Vcc
    +2Vtn(スレツシヨルド電位)になる様に設
    定したことを特徴とする請求項1記載のワード線
    リミツタ回路。
JP8376789U 1989-07-17 1989-07-17 Pending JPH0323896U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8376789U JPH0323896U (ja) 1989-07-17 1989-07-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8376789U JPH0323896U (ja) 1989-07-17 1989-07-17

Publications (1)

Publication Number Publication Date
JPH0323896U true JPH0323896U (ja) 1991-03-12

Family

ID=31631710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8376789U Pending JPH0323896U (ja) 1989-07-17 1989-07-17

Country Status (1)

Country Link
JP (1) JPH0323896U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007113746A (ja) * 2005-10-21 2007-05-10 Taifurekkusu Kk 接続継手

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60247899A (ja) * 1984-05-22 1985-12-07 Nec Corp 電気的書込み・消去可能不揮発性半導体メモリ
JPS61113195A (ja) * 1984-11-07 1986-05-31 Hitachi Ltd 半導体記憶装置
JPS6459100A (en) * 1987-08-28 1989-03-06 Seiko Instr & Electronics Deflecting magnet
JPH01173500A (ja) * 1987-12-28 1989-07-10 Toshiba Corp 不揮発性半導体記憶装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60247899A (ja) * 1984-05-22 1985-12-07 Nec Corp 電気的書込み・消去可能不揮発性半導体メモリ
JPS61113195A (ja) * 1984-11-07 1986-05-31 Hitachi Ltd 半導体記憶装置
JPS6459100A (en) * 1987-08-28 1989-03-06 Seiko Instr & Electronics Deflecting magnet
JPH01173500A (ja) * 1987-12-28 1989-07-10 Toshiba Corp 不揮発性半導体記憶装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007113746A (ja) * 2005-10-21 2007-05-10 Taifurekkusu Kk 接続継手

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