JPH0352036A - Pseudo fault circuit - Google Patents

Abstract

PURPOSE:To make a check by providing plural various error holding circuits and an error writing circuit which implants an error by a bus connecting the error holding circuits in series. CONSTITUTION:The error holding circuits 10, 20, 30 - n0 are so constituted that shift paths 101, 201, 301 - n01 are selected as input with an error write/read signal 211 and the values are inputted with trailing edges of clock signals 214. When (n) clock signals 214 are inputted in this state, an optional value from an implanted data signal 217 can be set in the error holding circuits 10, 20, 30 - n0. Error reading operation is carried out in this state to check whether error information is equal to the written value or not. Consequently, the normalcy of error reading operation and the error holding circuits 10, 20, 30 - n0 can be checked.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a simulated fault circuit. [Prior Art] Conventionally, in an information processing device, error information detected in the information processing device is serially read out using a diagnostic command, etc., and a circuit for storing error information (hereinafter referred to as EIF), processing after an error occurs, and a circuit for storing error information. The normality of the read operation itself can be checked by simulating errors in the error information one by one, or if the device has a scan path for the entire device and is equipped with a shift operation,
EIF was incorporated into the scan path and checked by shift operation. [Problems to be Solved by the Invention] In the conventional checking technology such as the EIF described above, in which error information is checked one by one, false fault circuits are required for each error information, and the number of circuits increases. Furthermore, the technique of checking by the shift operation of the entire device has the drawback that some small and medium-sized information processing devices do not have a shift operation in the device, and cannot be checked. [Means for Solving the Problems] The pseudo-failure circuit of the present invention includes a plurality of various error holding circuits and an error writing circuit that adds errors through a path that serially connects these error holding circuits. [Example] Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 1 shows an example implemented in an information processing device that holds n pieces of error information and serially reads out the error information. The error holding circuits 10, 20, 30, -nO receive shift path signals 101, 201, 301, . . . no1 and error signals 102, 202, 302, . -n02, error-1 read/write signal 211 and clock signal 214 are received, and when error-1 read/write signal 211 is logic "O", error signals 102, 202, 302, . . . no2 are set to logic "1".
”, shift pass signal 101, 201, 301, =-
No. 1 is taken in at the rising edge of the clock signal 214, and shift pass signals 201, 301, . . . no. 1 and an error-read data signal 215 are output, respectively. The shift data switching circuit 11 receives an error read data signal 215 and an error write data signal 216, and outputs an error write signal 2.
10 and output as a shift path signal 101.

The error write circuit 12 receives an embedded data signal 217 and a control signal 218 when reading an error or writing an error, and outputs an error write data signal 216, an error write signal 210 . Outputs error-read/write signal 211. The clock switching circuit 13 receives the normal clock 212, the diagnostic clock 213, and the error-read/write signal 211, and switches the normal clock 212 when the error-read/write signal 211 is logic "ON", and switches it to the diagnostic clock when the error-read/write signal 211 is logic "1". Clock 213 is selected and output as clock signal 214. Next, the operation of this circuit will be explained.

During normal operation, the error read/write signal 211 is logic “0”.
'', the normal clock 21 is set by the clock switching circuit 13.
2 is selected and output as the clock signal 214. In addition, in the error holding circuit 10.20, 30, -・no,
Error signals 102, 202, 302, -n02 are selected as inputs, and if an error occurs, the clock signal 21
It is in a state where it is taken in at the rising edge of 4. During the error-read operation, the error-read write signal 21
1 is logic "1" and the clock switching circuit 13 outputs the diagnostic clock 213 as the clock signal 214. Also, the error write signal is logic "O" and the shift data switching circuit 11 selects the error read data signal 215. It is output as a shift pass signal 101. In the error holding circuit 10, 20, 30, = -nO, shift pass signals 101, 201, 301, -no1 are selected as inputs, and shift pass signals 201, 301, 401 are output by the rising edge of the clock signal 214. ..., n01,
Outputs error-read data signal 215. The read data of the error information is transmitted by the error read data signal 215, but n clock signals 214 are outputted so that all the information is transmitted. Furthermore, since the error read data signal 215 is input to the error holding circuit 10 via the shift data switching circuit 11, when n clock signals 214 are input, the error holding circuit 10,
20, 30, . . . no return to the state before the error-read operation, so that the error information will not be erased by the error-read operation. And here, the error read operation and error holding circuit 10
, 20, 30, . , . . . The value set to no is output as the error write data signal 216, and the error write signal 210 is set to logic "1" so that the shift data switching circuit 11 selects the error write data signal 216 as the shift pass signal 101. .

Error holding circuit 10.20,30. =-no is an error - shift path 101, 201 due to read/write signal 211
, 301. ---. No. 1 is selected as the input, and the value is taken in by the falling edge of the clock signal 214. In this state, when n clock signals 214 are input, any value from the embedded data signal 217 can be set in the error holding circuits 10, 20, 30, . . . no. From this state, perform an error read operation and check whether the data is the same as the written value.
...The normality of no can be checked.

Alternatively, by returning to normal operation from this state, it is possible to check the normality of processing after a buried error occurs.

〔Effect of the invention〕

As explained above, by providing two means for arbitrarily setting values in the circuits that store various types of error information, the circuits that store various types of error information, the operation of reading the error information, and the processing after the occurrence of various types of errors are performed. This has the advantage of being able to achieve normality with a simple circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1 0.20.30, ~, no-・L error holding circuit,
11... Shift data switching circuit, 12... Error writing circuit, 13... Clock switching circuit, 101, 2
0 1, 3 0 1. ~, n 0 1 =-
Shift path signal, 102, 202, 302. ~,n0
2-...Error signal, 210...Error write signal,
211...Error read/write signal, 212...Normal clock, 213...Diagnostic clock, 214...
...Clock signal, 215...Error read data signal, 216...Error write data signal, 217...
-Embedded data signal, 218...control signal.

Claims (1)

[Claims] A pseudo-failure circuit having a plurality of various error holding circuits and an error writing circuit that adds errors through a path serially connecting the error holding circuits.