JPH032635U - - Google Patents

Info

Publication number
JPH032635U
JPH032635U JP6254489U JP6254489U JPH032635U JP H032635 U JPH032635 U JP H032635U JP 6254489 U JP6254489 U JP 6254489U JP 6254489 U JP6254489 U JP 6254489U JP H032635 U JPH032635 U JP H032635U
Authority
JP
Japan
Prior art keywords
wiring board
insulating substrate
bonding pad
printed wiring
bare chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6254489U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6254489U priority Critical patent/JPH032635U/ja
Publication of JPH032635U publication Critical patent/JPH032635U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】
第1図イないしハは本考案における一実施例概
略構成図、第2図イおよびロは従来例説明図であ
る。 1……印刷配線板、2……ダイランド、3……
ベアチツプ、4……ボンデイング・パツド、5…
…ワイヤー、6……プツシユ・バツク可能な絶縁
基板、7……開口。

Claims (1)

  1. 【実用新案登録請求の範囲】 絶縁基板上に回路、ダイランド2、およびボン
    デイング・パツド4が形成されている印刷配線板
    1において、 当該印刷配線板1の一部を打ち抜いてプツシユ
    ・バツク可能な状態に嵌め込まれている絶縁基板
    6と、 当該プツシユ・バツク可能な絶縁基板6上に設
    けられたダイランド2と、 当該ダイランド2上に載置されている半導体ベ
    アチツプ3と、 当該半導体ベアチツプ3と上記印刷配線板1の
    ボンデイング・パツド4とを接続するワイヤー5
    と、 半導体ベアチツプ3、ボンデイング・パツド4
    およびワイヤー5の部分をモールドする樹脂と、 からなることを特徴とする印刷配線板。
JP6254489U 1989-05-31 1989-05-31 Pending JPH032635U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6254489U JPH032635U (ja) 1989-05-31 1989-05-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6254489U JPH032635U (ja) 1989-05-31 1989-05-31

Publications (1)

Publication Number Publication Date
JPH032635U true JPH032635U (ja) 1991-01-11

Family

ID=31591791

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6254489U Pending JPH032635U (ja) 1989-05-31 1989-05-31

Country Status (1)

Country Link
JP (1) JPH032635U (ja)

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