JPH03268596A - Rgb video signal transmission system - Google Patents

Abstract

PURPOSE:To transmit each digital video signal through one signal line and to prevent the generation of flickering on a display picture by converting R, G and B digital video signals into step-like waveform voltage signals by voltage modulation and demodulating the step-like waveform voltage signals correspondingly to respective colors by an input circuit on the display device side. CONSTITUTION:The n-bit digital signals of red(R), blue(B) and green(G) are generated by a video data generating circuit 1a and outputted as step-like waveform voltage signals through a data conversion circuit 1b. Namely, an interval between the high and low levels of each digital signal out of R, G and B digital signals is divided into 2n-1 and 2n-1 step-like waveform voltage signals are respectively individually outputted and respective voltage signals Red, Gre, Blu are transmitted to respective input circuits 2, 3, 4, of a picture display device respectively through signal lines 5 to 7 correspondingly to each line. The input circuit 2 changes the reference voltage Vf of a comparator 21 by (2n-1) times the dot clock, the voltage level of each change is set up to the intermediate position level of respective level difference rise of each step-like waveform voltage signals and the output of the comparator is converted into an n-bit digital signal.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a system for transmitting RGB video signals from, for example, a computer to a display device.

<Prior Art> Conventionally, as image signals output from a computer to a display device such as a CRT, there have been digital RGB separator video signals and analog RGB video signals. In recent years, in addition to CRT, LCD, FDP, and EL have been used as display devices.
In order to display these panels in color and to display color gradation, multiple bits of R, G, and B digital signals are required depending on the number of gradations. .

<Problems to be Solved by the Invention> Incidentally, in order to input a plurality of bits of R, G, and B digital signals to a flat panel display device, it has conventionally been necessary to input digital R, G, and B video signals from a computer or the like through a plurality of vias. Either transmit each signal in parallel, or transmit the analog RGB video signal to a flannel panel display, within which the input analog signal is A/
Methods such as D conversion have been adopted, but the former method requires signal lines corresponding to the number of bits of each R'G and B digital signal, resulting in an extremely large number of signal lines. There is a problem. On the other hand, according to the latter method, only one signal line each for R, G, and B is required, but
/ Since the analog signal near the threshold voltage of the D converter contains an error in the converted digital value, there is a problem in that the displayed image flickers.

<Means for Solving the Problems> The present invention has been made to solve the above-mentioned conventional problems, and the configuration thereof will be explained with reference to FIG. 1 corresponding to an embodiment. n of each color of R and CB
A system for transmitting a bit digital video signal, which generates n-bit R2O and B digital signals, converts each digital signal into a voltage signal with a stepped waveform of (2n-1) stages, and outputs it. It has a processing device (computer) 1 and an input circuit 2.3.4 that inputs each analog signal from the processing device 1, and each input circuit has a comparator 21 and a reference voltage of the comparator 210. , a setting circuit that changes the voltage level with a clock that is (2"-1) times the dot clock, and sets the voltage level for each change to the level of the intermediate position of each step rise of the stepped waveform voltage signal. It is characterized by being constituted by means (ternary counter 26, etc.) and a conversion circuit (for example, D flip-flops 123, 24, latch circuit 25, encoder 22, etc.) that creates an n-bit digital signal from the output of comparator 1. can be attached.

Note that the term "don't clock" as used in the present invention refers to a basic clock of a video signal having a period of one pixel.

<Operation> First, the R, G, and B video signals are independent.
Since each of the transmission systems only needs to be provided with three identical transmission systems in parallel, only the R signal will be explained.

When expressing 2n red gradations from a multi-bit R video signal, for example, an n-bit R signal, the n-bit R signal is processed by voltage modulation in the processing device 1 to create a voltage with a stepped waveform of 2 g/1 step. The stepped voltage signal Red is converted into a signal Red, and the stepped voltage signal Red is transmitted through one R signal line 5. This transmitted signal Red is taken into the input circuit 2 and the comparator 2
The reference voltage Vf of this comparator is set to 1/2 level of the wave height at the stepped portion of the stepped voltage signal by the setting circuit.
It changes sequentially at a high speed clock of 2''-1) times, thereby making it possible to obtain one comparator output of 2''. Then, by encoding the comparator output by the next stage circuit, an n-bit digital R signal is reproduced.

<Example> Embodiments of the present invention will be described below based on concave surfaces.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

First, in the embodiment of the present invention, a transmission system for 2-bit digital R, G, and B video signals will be described for the sake of simplicity.

Red, blue, and green 2-bit digital signals R9 and Rφ, G1 and Gφ, B1 and Bφ are generated by a video data generation circuit 1a controlled by programming inside the computer 1. Furthermore, the data conversion circuit 1b of the computer 1 sets each of the R, G, and B 2-bit digital signals to a level corresponding to the display content and outputs them as stepped waveform voltage signals. In other words, in order to express 2n gradations of each color, the distance between the old GH level (+5V) and the L level (OV) of each digital R, G, and B is divided into 2n-1, and 2"-1 steps, that is, 3 The stepwise waveform voltage signals of each stage are individually output, and each voltage signal R
ed+Gre and Blue are transmitted to the input circuits 2 and 3.4 of the image display device (not shown) through negative signal lines 5 and 6.7, respectively. Each input circuit 2, 3.4
Both have the same circuit configuration, and henceforth, only the input circuit 2 for the Red signal will be explained.

The input circuit 2 includes one comparator 21 that compares the Red signal with a reference voltage Vf to be described later, two D flip-flops 23 and 24, a latch circuit 25, and an encoder 22 connected in sequence to the output side of the comparator 21. . Further, the input circuit 2 is provided with a ternary counter 26, and the ternary counter 26 and the latch circuit 25 are provided with 1/(2"-1) of the dot clock of the digital R signal, that is, 1
A clock pulse of /3 is inputted to the launch circuit 25, and an inverted signal LP of the output QB of the ternary counter 26 is inputted to the launch circuit 25.

On the other hand, the reference voltage Vf of the comparator 21 is determined by the transistors 27a and 27b that turn 0N10FF according to the outputs QA and QB of the ternary counter 26, and the three resistors 2B-2.
8, V thh, V thm, V
The level of thl is sequentially set at a cycle of 1/3 of the dot clock.

FIG. 2 is a timing chart of an embodiment of the present invention.
The operation and effect of each part will be explained with reference to this figure.

The 2-bit digital videos R and Rφ have wave heights VRφI+VRI, VH2 inside the computer 1.
A four-stage stepped voltage signal Red of .degree.VH3 is transmitted to the input circuit 2 through the negative R signal lines 5, where the levels are compared by the comparator 21. The reference voltage Vf of the comparator 21 is 1/1 of the dot clock.
This reference voltage v thhV changes sequentially to V thh, V thm, and V thl in the period of 3.
By setting thm and V thl to levels at 1/2 of the rising wave height of the stepped waveform voltage, the output of the comparator 21 is . becomes a waveform signal as shown in the figure. This signal ■. is input to the latch circuit 25, but
At this time, the signals ■.1 and v02, which are delayed by 1 and 2 clock pulses with respect to the signal ■., are also input to the latch circuit 25 by the two D flip-flops 23'' and 24.The launch circuit 25 At the rising edge of the clock pulse when the signal LP is at a low level, the signals ■., ■.1 and ■.2 are latched, respectively, and thereby the signals RL, RM, and RH are input to the encoder 22. This signal RL is ``■'' when the reference voltage Vf of the comparator 21 is Vthl, RM is ``■'' when the reference voltage Vf of the comparator 21 is V thm, and RH is V th.
■ for h hour. will be shown respectively. These three signals RL, RM, and RH are then binarized by the encoder 22 to become 2-bit digital signals RD and RDφ. These RD, , RDφ have waveforms as shown in the figure, and the same digital signals as the 2-bit digital video signals R, , Rφ input to the computer 1 are reproduced on the display device side with a delay of one dot clock. That will happen. As for the G and B signals, as well as the R signal, the C
D, , GDφ and BD, , BDφ will be reproduced.

From the above, even if there is only one R signal line, it is possible to display an image equivalent to that obtained when 2-bit digital video signals are transmitted in parallel. Moreover, the same can be said for the G signal and the B signal as for the R signal, and each of the R, G, and B 2-bit digital video signals is transmitted through one signal line each, a total of three signal lines. becomes possible.

According to the embodiment of the present invention, each of the input circuits 2, 3 and 4 only needs to be provided with one comparator, and furthermore, the circuits after the comparator (the portion indicated by the broken line in FIG. 1) are all digital. Since all of these circuits can be integrated into LSI, it is possible to reduce the size and cost of the input circuit.

In the embodiment of the present invention described above, each of R, G, and B 2-bit digital video signals are processed in the computer 1.
Voltage signals Red and Gre with stepped wave heights.

Although it is converted to Btu, for example, a current addition type D/A conversion circuit using an operational amplifier or R-2R
Each digital video signal may be converted using a general circuit such as a D/A conversion circuit using a ladder circuit.

Further, the present invention is also applicable to digital video signals of arbitrary plural bits of two or more dots. In this case, although the number of stages of the stepped voltage signal increases and the number of reference voltage settings for the comparator increases accordingly, only one signal line is required for each of the R, G, and B digital signals. , only one comparator is required for each digital signal.

<Effects of the Invention> As explained above, according to the present invention, n-bit R,
The G and B digital video signals are each converted into step waveform voltage signals by voltage modulation, and the step waveform voltage signals are demodulated in correspondence with each color in an input circuit on the side of a display device such as a flat panel. Therefore, R, G, B
digital video signals can be transmitted by each - signal line. Moreover, conventional analog RGB
When A/D converting analog signals on the display device side, which has been a problem in video signal transmission systems,
The problem that the analog signal near the threshold voltage includes an error in the converted digital value is also eliminated, and the flickering of the displayed image is also eliminated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
The figure is a timing chart showing the operation of this embodiment. 1 ・ 2, 3. 4 ・ 21 ・ 22 ・ 23 24 ・ 25 ・ 26 ・ 27a, 27b ・ 28...28 ・ 5, 6. 7. Computer input circuit comparator encoder D flip-chip latch circuit ternary counter transistor resistance signal line

Claims (1)

[Claims] A system for transmitting n-bit digital video signals of each color of R, G, and B, wherein the n-bit R
, G, and B digital signals, converts each digital signal into a stepped waveform voltage signal, and outputs it, and an input circuit that inputs each analog signal from the processing device. Each input circuit connects a comparator and the reference voltage of that comparator to
a setting circuit means for changing the voltage at a clock rate (2^n-1) times the clock, and setting the voltage level for each change to a level at an intermediate position of each step rising edge of the stepped waveform voltage signal; An RGB video signal transmission system comprising a conversion circuit that converts the output of a comparator into an n-bit digital signal.