JPH03270233A - 金属配線層の平坦化方法 - Google Patents

金属配線層の平坦化方法

Info

Publication number
JPH03270233A
JPH03270233A JP2070897A JP7089790A JPH03270233A JP H03270233 A JPH03270233 A JP H03270233A JP 2070897 A JP2070897 A JP 2070897A JP 7089790 A JP7089790 A JP 7089790A JP H03270233 A JPH03270233 A JP H03270233A
Authority
JP
Japan
Prior art keywords
wiring layer
metal wiring
alignment mark
film
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2070897A
Other languages
English (en)
Japanese (ja)
Inventor
Ryoichi Mukai
良一 向井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2070897A priority Critical patent/JPH03270233A/ja
Priority to US07/671,227 priority patent/US5100834A/en
Priority to EP91400759A priority patent/EP0448471B1/de
Publication of JPH03270233A publication Critical patent/JPH03270233A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/04—Planarisation of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/093—Laser beam treatment in general
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
JP2070897A 1990-03-20 1990-03-20 金属配線層の平坦化方法 Pending JPH03270233A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2070897A JPH03270233A (ja) 1990-03-20 1990-03-20 金属配線層の平坦化方法
US07/671,227 US5100834A (en) 1990-03-20 1991-03-19 Method of planarizing metal layer
EP91400759A EP0448471B1 (de) 1990-03-20 1991-03-20 Verfahren zur Herstellung eines Halbleiterbauelementes mit einer Planarisierung einer Metallschicht

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2070897A JPH03270233A (ja) 1990-03-20 1990-03-20 金属配線層の平坦化方法

Publications (1)

Publication Number Publication Date
JPH03270233A true JPH03270233A (ja) 1991-12-02

Family

ID=13444783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2070897A Pending JPH03270233A (ja) 1990-03-20 1990-03-20 金属配線層の平坦化方法

Country Status (3)

Country Link
US (1) US5100834A (de)
EP (1) EP0448471B1 (de)
JP (1) JPH03270233A (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6350680B1 (en) * 2000-05-26 2002-02-26 Taiwan Semiconductor Manufacturing Company Pad alignment for AlCu pad for copper process

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04122012A (ja) * 1990-09-12 1992-04-22 Mitsubishi Electric Corp アライメントマークおよびその形成方法
JPH05109715A (ja) * 1991-10-16 1993-04-30 Nec Corp 半導体装置の製造方法
JP3332456B2 (ja) * 1992-03-24 2002-10-07 株式会社東芝 半導体装置の製造方法及び半導体装置
US5911108A (en) * 1997-01-29 1999-06-08 Integrated Device Technology, Inc. Method for protecting an alignment mark on a semiconductor substrate during chemical mechanical polishing and the resulting structure
US6100157A (en) 1998-06-22 2000-08-08 Oki Electric Industry Co., Ltd. Formation of alignment mark and structure covering the same
JPH1126361A (ja) * 1997-06-27 1999-01-29 Oki Electric Ind Co Ltd アライメントマーク及びアライメントマーク用凹部の隠蔽方法
EP0892433A1 (de) * 1997-07-15 1999-01-20 International Business Machines Corporation Herstellungsverfahren für eine Ausrichtungsmarkierung in einer Halbleiterstruktur
JP2000021737A (ja) * 1998-07-07 2000-01-21 Mitsubishi Electric Corp 位置合わせマークおよびその製造方法
US6979526B2 (en) * 2002-06-03 2005-12-27 Infineon Technologies Ag Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs
US6858441B2 (en) * 2002-09-04 2005-02-22 Infineon Technologies Ag MRAM MTJ stack to conductive line alignment method
US7442624B2 (en) * 2004-08-02 2008-10-28 Infineon Technologies Ag Deep alignment marks on edge chips for subsequent alignment of opaque layers

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4388517A (en) * 1980-09-22 1983-06-14 Texas Instruments Incorporated Sublimation patterning process
JPS592352A (ja) * 1982-06-28 1984-01-07 Toshiba Corp 半導体装置の製造方法
JPS61102723A (ja) * 1984-10-26 1986-05-21 Fujitsu Ltd 半導体装置の製造方法
JPS61256635A (ja) * 1985-05-09 1986-11-14 Nec Corp 半導体装置の製造方法
JPS6327013A (ja) * 1986-07-18 1988-02-04 Nec Corp 半導体装置の製造方法
JPS6341020A (ja) * 1986-08-06 1988-02-22 Nec Corp 半導体装置の製造方法
JPS63160330A (ja) * 1986-12-24 1988-07-04 Mitsubishi Electric Corp マスクアライメントの方法
US4920070A (en) * 1987-02-19 1990-04-24 Fujitsu Limited Method for forming wirings for a semiconductor device by filling very narrow via holes
JPS63215055A (ja) * 1987-03-04 1988-09-07 Hitachi Ltd 半導体装置の配線形成方法
US4893163A (en) * 1988-03-28 1990-01-09 International Business Machines Corporation Alignment mark system for electron beam/optical mixed lithography
JPH0227711A (ja) * 1988-07-15 1990-01-30 Sanyo Electric Co Ltd 半導体装置の製造方法
JPH02137344A (ja) * 1988-11-18 1990-05-25 Nec Corp 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6350680B1 (en) * 2000-05-26 2002-02-26 Taiwan Semiconductor Manufacturing Company Pad alignment for AlCu pad for copper process

Also Published As

Publication number Publication date
EP0448471A3 (en) 1993-05-26
EP0448471B1 (de) 1998-07-29
EP0448471A2 (de) 1991-09-25
US5100834A (en) 1992-03-31

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