JPH03282917A - Interface circuit - Google Patents

Abstract

PURPOSE:To connect a peripheral device whose signal logical level is inverted only by the change of specification by storing a signal converted by a signal control register and its inverted signal in a buffer and specifying either one of the signals. CONSTITUTION:The interface circuit is provided with a control signal level specifying circuit 4 consisting of two buffers 8, 9, two inverters 6, 7 and a level specifying register 5. A microprocessor (MP) 1 converts an input signal from a master device through an address decoder 2 and a signal control register 3, stores the converted signal in a buffer 8 as an intermediate signal (e), inverts the logical level of the signal (e) by the inverter 6 and stores the inverted signal in the buffer 9 as an inverted intermediate signal (g). When '0' is written from the MP1 in the register 5 through an address bus (a), a control signal line (b) and a data bus (c) prior to the connection of the peripheral device 10, the signal (e) is outputted by an output control signal (j), and in the case of writing '1', the signal (g) is outputted by an inverted level specifying signal (i). Thereby, even when the signal level of the peripheral device 10 is changed, the device 10 can be connected only by changing the specification.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interface circuit between a host device and a peripheral device of an information processing device.

[Conventional technology 1] Conventionally, signals in interface circuits with peripheral devices have been standardized in a logical format by combinations of valid and invalid (l and 0); Which one is disabled differs for each peripheral device, and the interface circuit is designed in accordance with the specifications of each peripheral device.

[Problem to be Solved by the Invention] The conventional interface circuit described above is designed to correspond to the valid level of the signal of the peripheral device, so when the specifications of the peripheral device change, the valid/invalid level simply changes. Even if it is only inverted, the disadvantage is that the entire interface circuit must be changed.

An object of the present invention is to provide an interface circuit that can set the effective level of a signal to either high or low.

[Means for Solving the Problems] An interface circuit of the present invention includes: an inverter circuit that inverts the logic level of a signal converted by the signal control register; a buffer in which the signal converted by the signal control register is stored; A buffer that stores a signal inverted by the inverter circuit; and a level designation register that designates one of the signals stored in the two buffers as a control signal to be output to the peripheral device. It has a control signal level designation circuit.

[Operation] The interface circuit of the present invention stores two signals, a signal converted by a signal control register and a signal inverted by an inverter circuit, in a buffer, and controls one of the signals by a level specifying register. Since it can be specified, when the logic level of a signal of a peripheral device is inverted, the peripheral device can be connected simply by changing the designation of the level specification register.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the interface circuit of the present invention.

The interface circuit of this embodiment includes two buffers 8,
9, two inverter circuits 6 and 7, and a level designation register 5.The microprocessor l receives a human input signal from a host device by an address decoder 2 and a signal control register 3. The signal is converted and stored in a buffer 8 as an intermediate signal e, and the logic level of the intermediate signal e is inverted by an inverter 6 and stored in a buffer 9 as an inverted intermediate signal g. On the other hand, the microprocessor 1 outputs an output enable signal (level designation signal or inverted level designation signal l) from the level designation register 5 to either the buffer 8 or the buffer 9.
The settings are made as shown in Table 1 in accordance with the logic level specification of the control signal J of the peripheral device 10 so as to send the signal J.

Table 1 In other words, before connecting the peripheral device 10, from the microprocessor l to the address bus a and the control signal line b
, “0” is sent to the level specification register 5 through the data bus C.
By writing , the level designation signal h (
=o) is sent as the output enable signal, the intermediate signal e stored in the buffer 8 is output as the output control signal j, and when "1" is written in the level designation register 5,
Since the inverted level designation signal i (0=1) inverted by the inverter 7 is sent to the buffer 9, the inverted intermediate signal g
is output.

[Effects of the Invention] As explained above, the present invention includes an inverter circuit that inverts the output level of a control signal in an interface circuit, and specifies the level of a control signal output to a peripheral device as either non-inverted or inverted. By providing a control signal level designation circuit consisting of a control signal level designation register, if the effective level of an interface signal is inverted due to a change in the specifications or model of a peripheral device, the designation of non-inverted/inverted can be changed. This makes it possible to connect the peripheral devices using the same interface circuit, which has the effect of making design and manufacturing more economical.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the interface circuit of the present invention. 1...-Microprocessor, 2...-Address decoder, 3...-Signal control register, 4...Control signal level designation circuit, 5...Level designation register, 6.7...Inverter circuit, 8 ,9...-Buffer, IO...Peripheral device, a...Address, b...Control signal, C...-Data, d, f...Write signal, e...Intermediate signal, g ...Inverted intermediate signal, h--Level designation signal, l...Inverted level designation signal, J--Peripheral device control signal.

Claims (1)

[Claims] 1. In an interface circuit in which a microprocessor converts a signal input from a host device using a signal control register and outputs a control signal to a peripheral device, the logic level of the signal converted by the signal control register is an inverter circuit that inverts the signal, a buffer that stores the signal converted by the signal control register, a buffer that stores the signal that is inverted by the inverter circuit, and a signal stored in the two buffers, An interface circuit comprising a control signal level designation circuit including a level designation register that designates one of the signals as a control signal to be output to the peripheral device.