JPH0350295B2 - - Google Patents

Info

Publication number
JPH0350295B2
JPH0350295B2 JP62501223A JP50122387A JPH0350295B2 JP H0350295 B2 JPH0350295 B2 JP H0350295B2 JP 62501223 A JP62501223 A JP 62501223A JP 50122387 A JP50122387 A JP 50122387A JP H0350295 B2 JPH0350295 B2 JP H0350295B2
Authority
JP
Japan
Prior art keywords
command
execution
condition
conditional branch
order
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62501223A
Other languages
English (en)
Japanese (ja)
Other versions
JPH01500066A (ja
Inventor
Dagurasu Daburyu Kuraaku
Deburaa Baansutain
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of JPH01500066A publication Critical patent/JPH01500066A/ja
Publication of JPH0350295B2 publication Critical patent/JPH0350295B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
JP62501223A 1986-01-29 1987-01-29 ブランチ指令を実施するための方法 Granted JPH01500066A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US82377686A 1986-01-29 1986-01-29
US823,776 1986-01-29

Publications (2)

Publication Number Publication Date
JPH01500066A JPH01500066A (ja) 1989-01-12
JPH0350295B2 true JPH0350295B2 (fr) 1991-08-01

Family

ID=25239679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62501223A Granted JPH01500066A (ja) 1986-01-29 1987-01-29 ブランチ指令を実施するための方法

Country Status (5)

Country Link
EP (1) EP0290465A1 (fr)
JP (1) JPH01500066A (fr)
AU (1) AU7021387A (fr)
CA (1) CA1285657C (fr)
WO (1) WO1987004821A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6341932A (ja) * 1985-08-22 1988-02-23 Nec Corp 分岐命令処理装置
JPH01283635A (ja) * 1988-05-11 1989-11-15 Nec Corp バッファ制御回路
SE510295C2 (sv) * 1997-07-21 1999-05-10 Ericsson Telefon Ab L M Metod vid processor för att hantera villkorade hoppinstruktioner samt processor anpassad att verka enligt den angivna metoden

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
JPS56140445A (en) * 1980-04-01 1981-11-02 Hitachi Ltd Information processing device
US4373180A (en) * 1980-07-09 1983-02-08 Sperry Corporation Microprogrammed control system capable of pipelining even when executing a conditional branch instruction
JPS57153342A (en) * 1981-03-19 1982-09-21 Mitsubishi Electric Corp Pipeline computer
JPS6049339A (ja) * 1983-08-30 1985-03-18 Dainippon Screen Mfg Co Ltd 複製画像の編集装置
US4742451A (en) * 1984-05-21 1988-05-03 Digital Equipment Corporation Instruction prefetch system for conditional branch instruction for central processor unit

Also Published As

Publication number Publication date
CA1285657C (fr) 1991-07-02
AU7021387A (en) 1987-08-25
EP0290465A1 (fr) 1988-11-17
WO1987004821A1 (fr) 1987-08-13
JPH01500066A (ja) 1989-01-12

Similar Documents

Publication Publication Date Title
US5325495A (en) Reducing stall delay in pipelined computer system using queue between pipeline stages
US5235686A (en) Computer system having mixed macrocode and microcode
US4594659A (en) Method and apparatus for prefetching instructions for a central execution pipeline unit
EP0378425A2 (fr) Dispositif d'exécution d'instructions de branchement
JPH0115093B2 (fr)
JPH02257219A (ja) パイプラインプロセッサ装置および方法
JPH06236271A (ja) プロセッサおよび命令推測実行方法
US6959004B2 (en) Data driven information processing apparatus
EP0730223B1 (fr) Dispositif de traitement de données du type pipeline pour l'exécution d'une pluralité de processus de données ayant des dépendances de données entre eux
JPH0139132B2 (fr)
EP0592404A1 (fr) Appareil et procede d'obtention d'une ante-memoire a blocage
EP0497485A2 (fr) Ordinateur pour la mise en oeuvre des instructions à deux opérandes
US20040054950A1 (en) Apparatus and method for device selective scans in data streaming test environment for a processing unit having multiple cores
JPH0350295B2 (fr)
JPS63228225A (ja) ディジタルコンピュータシステム
US4794527A (en) Microprogrammed data processing system using latch circuits to access different control stores with the same instruction at different times
CN105446700B (zh) 一种指令执行方法以及顺序处理器
JPS62117039A (ja) コントロ−ラ
JPH04215129A (ja) 連続指令実行方法及び装置
EP0500193A1 (fr) Dispositif et méthode pour exécution des instructions de branchement
US7130988B2 (en) Status register update logic optimization
KR910001055B1 (ko) 파이프라인방식으로 처리되는 데이터처리시스템에 있어서 트랩된 마이크로어드레스의 재배열방법 및 그 장치
JP2000194556A (ja) 命令ルックアヘッドシステムおよびハ―ドウェア
JP3955843B2 (ja) マイクロプロセッサの並列シミュレーションシステム
JPS59183434A (ja) 命令先取り制御方式