JPH0360007A - Clad sio substrate - Google Patents
Clad sio substrateInfo
- Publication number
- JPH0360007A JPH0360007A JP19462389A JP19462389A JPH0360007A JP H0360007 A JPH0360007 A JP H0360007A JP 19462389 A JP19462389 A JP 19462389A JP 19462389 A JP19462389 A JP 19462389A JP H0360007 A JPH0360007 A JP H0360007A
- Authority
- JP
- Japan
- Prior art keywords
- silicon wafer
- thickness
- oxide film
- silicon
- element forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
表面に酸化膜を形成されたシリコンウェハを重ね合わせ
て接着したあと素子形成側シリコンウェハバをSi化し
た、いわゆる張合わせ5ot(Siticon on
1nsulatar >基板に関し、素子形成側シリコ
ンウェハの厚さを1μ憎未満のWAssにした場合にこ
の素子形成側シリコン及びその酸化膜の剥離を防止する
ことを目的とし、
素子形成側シリコンウェハに形成された酸化膜の厚さを
、素子形成側シリコンウェハの厚さ未満に形成した構成
とする。[Detailed Description of the Invention] [Summary] Silicon wafers with an oxide film formed on their surfaces are stacked and bonded together, and then the silicon wafer bar on the element forming side is converted to Si, so-called bonded 5ot (Siticon on
1 nsulatar >Regarding the substrate, when the thickness of the silicon wafer on the element formation side is set to WAss of less than 1 μm, the purpose of preventing the peeling of the silicon on the element formation side and its oxide film is to form on the silicon wafer on the element formation side. The thickness of the oxide film formed is less than the thickness of the silicon wafer on the element formation side.
本発明は、表面に酸化膜を形成されたシリコンウェハを
重ね合わせて接着したあと素子形成側シリコンウェハを
薄膜化した、いわゆる張合わせSOI基板に関する。The present invention relates to a so-called bonded SOI substrate in which silicon wafers having an oxide film formed on their surfaces are stacked and bonded together, and then the silicon wafer on the element forming side is thinned.
張合わせSol基板は素子形成側シリコンウエ八と支持
基板側シリコンウェハとを酸化シリコン(S!Oz)等
の酸化膜を介して重ね合わせたもので、特に、この方法
によるとシリコンの結晶性をそのまま用いることができ
るので高性能のSOI基板を得ることができる。このよ
うなSol構造の基板は、素子形成側シリコンウェハの
厚さが薄い方が集積度や動作速度等の点で有利であるが
、このように薄い形成側シリコンウェハを用いたものは
、ウェハ裏面(即ち、素子形成側シリコンウェハと酸化
膜との界面)も電気的に活性な素子領域の一部となるた
めに素子形成側シリコンウェハと酸化膜との界面特性が
重要となり、又、素子形成側シリコンウェハ及び酸化膜
を受持基板側シリコンウェハに接着面から剥離すること
なく確実に保持できるような構成にしておくことが重要
である
〔従来の技術〕
張合わせSol基板は、例えば第3図に示す如く、素子
形成側シリコンウェハ1と支持基板側シリコンウェハ2
とを酸化膜3を介して重ね合わせた構成とされている。The bonded Sol substrate is made by laminating a silicon wafer on the element forming side and a silicon wafer on the support substrate side with an oxide film such as silicon oxide (S!Oz) interposed therebetween. In particular, this method improves the crystallinity of the silicon. Since it can be used as is, a high-performance SOI substrate can be obtained. For substrates with such a Sol structure, thinner silicon wafers on the element formation side are advantageous in terms of integration degree and operation speed. Since the back surface (i.e., the interface between the silicon wafer on the element formation side and the oxide film) also becomes part of the electrically active element region, the interface characteristics between the silicon wafer on the element formation side and the oxide film are important. It is important to have a structure that allows the silicon wafer on the forming side and the oxide film to be reliably held on the silicon wafer on the receiving substrate side without peeling off from the adhesive surface. As shown in Figure 3, a silicon wafer 1 on the element formation side and a silicon wafer 2 on the supporting substrate side
The structure is such that the two are overlapped with each other with an oxide film 3 interposed therebetween.
この場合、酸化膜3を形成するに際し、支持基板側シリ
コンウェハ2を熱酸化して形成した場合には酸化膜3の
上面3aが接着界面(リーク電流を生じる)となるので
素子形成側シリコンウェハ1の裏面(3a)を活性素子
領域として用いる超薄膜タイプ(素子形成側シリコンウ
ェハ1の厚さ1μm未満)のものでは良好な特性を得る
ことができないが、素子形成側シリコンウェハ1を熱酸
化して形成した場合には酸化膜3の下面3bが接着界面
となるので素子形成側シリコンウェハ1の裏面3aを活
性素子領域として用いる上記超11111タイプのもの
においてリーク電流が問題となることはない。In this case, when the oxide film 3 is formed by thermally oxidizing the silicon wafer 2 on the support substrate side, the upper surface 3a of the oxide film 3 becomes an adhesive interface (which causes leakage current), so the silicon wafer 2 on the element formation side Although it is not possible to obtain good characteristics with an ultra-thin film type (thickness of the silicon wafer 1 on the element formation side less than 1 μm) in which the back surface (3a) of the silicon wafer 1 is used as the active element region, thermal oxidation of the silicon wafer 1 on the element formation side In this case, the lower surface 3b of the oxide film 3 becomes the adhesive interface, so leakage current does not become a problem in the super 11111 type described above in which the back surface 3a of the silicon wafer 1 on the element forming side is used as the active element region. .
そこで、従来の超薄膜タイプの張合わt!sOI基板用
ウェハでは、素子形成側シリコンウェハのみ、或いは素
子形成側シリコンウェハ及び支持基板側シリコンウェハ
の両方に酸化膜を形成したものを用い、良好な界面特性
を得るようにしていた。Therefore, conventional ultra-thin film type lamination t! In sOI substrate wafers, oxide films are formed only on the element formation side silicon wafer, or on both the element formation side silicon wafer and the support substrate side silicon wafer, in order to obtain good interface characteristics.
この場合、従来の超薄膜タイプの張合わせSOI基板用
ウェハでは、一般に、酸化膜厚は0,5μ−で、この厚
さは素子形成側シリコンウェハ1の厚さとは無関係に定
められていた。In this case, in the conventional ultra-thin film type bonded SOI substrate wafer, the oxide film thickness is generally 0.5 .mu.-, and this thickness is determined regardless of the thickness of the silicon wafer 1 on the element forming side.
一般に、酸化シリコン(Si 02 )とシリコンとは
熱膨脹係数が1桁以上異なるため、薄膜化した場合には
酸化膜とシリコンウェハとのバランスが崩れて変形しよ
うとする応力がシリコンウェハに発生し、この応力は酸
化膜の厚さが厚い程、又、シリコンウェハの厚さが薄い
程強くなる。この応力の方向は、第3図中、シリ」ンウ
エハ接着界面3b方向と逆方向であるため、特に素子形
成側シリコンウェハ1が薄い場合には、素子形成側シリ
コンウェハ1及びその酸化膜3は支持基板側シリコンウ
ェハ2との接着界面3bから剥離してしまい、特に素子
形成側シリコンウェハ1の厚さが1μm未満の超薄膜タ
イプのものではその傾向が強い問題点があった(この現
象は、素子形成側シリコンウェハの厚さが1μm以上の
Sol基板では発生しなかった)。In general, silicon oxide (Si 02 ) and silicon have thermal expansion coefficients that differ by more than an order of magnitude, so when the film is made thinner, the balance between the oxide film and the silicon wafer is disrupted, causing stress in the silicon wafer that tends to deform it. This stress becomes stronger as the oxide film becomes thicker and the silicon wafer becomes thinner. Since the direction of this stress is opposite to the direction of the silicon wafer bonding interface 3b in FIG. There was a problem in that the silicon wafer 1 on the side of the element formation had a strong tendency to peel off from the adhesive interface 3b with the silicon wafer 2 on the support substrate side, especially in the case of an ultra-thin film type with a thickness of less than 1 μm (this phenomenon (This phenomenon did not occur in the case of a Sol substrate in which the thickness of the silicon wafer on the element formation side was 1 μm or more).
本発明は、素子形成側シリコンウェハの厚さを1a霞未
満の超薄膜にした場合にこの素子形成側シリコンの剥離
を防止し得る張合わせSol基板を提供することを目的
とする。An object of the present invention is to provide a bonded Sol substrate that can prevent peeling of the silicon on the element formation side when the thickness of the silicon wafer on the element formation side is made into an ultra-thin film of less than 1a haze.
第1図は本発明の原理図を示す。同図中、20は厚さ1
μm未満の薄膜化された素子形成側シリコンウェハ、2
1は支持基板側シリコンウェハ、22はこれらの間に設
けられた酸化膜で、酸化膜22は少なくとも素子形成側
シリコンウェハ20の表面に形成された酸化膜である。FIG. 1 shows a diagram of the principle of the present invention. In the same figure, 20 is the thickness 1
Element formation side silicon wafer with a thin film of less than μm, 2
1 is a supporting substrate side silicon wafer, 22 is an oxide film provided between these, and the oxide film 22 is an oxide film formed at least on the surface of the element forming side silicon wafer 20.
本発明は、素子形成側シリコンウェハ20に形成された
酸化膜22の厚さを、素子形成側シリコンウェハ20の
厚さ未満に形成してなる。In the present invention, the thickness of the oxide film 22 formed on the element forming side silicon wafer 20 is formed to be less than the thickness of the element forming side silicon wafer 20.
素子形成側シリコノウ1ハ20に形成された酸化膜22
の厚さが素子形成側シリコンウェハ20の厚さ未満であ
るため、素子形成側シリコンウェハ20の厚さが1μm
未満の超薄膜タイプのものでも、シリコン及び酸化シリ
コンの熱膨張係数の違いによってシリコンウェハに生じ
る応力は従来例のものよりも大幅に小さくできる。これ
により、素子形成側シリコンウェハ20の厚さが1μm
未満の超薄膜タイプのものでも素子形成側シリコンウェ
ハ20及び酸化膜22が支持基板側シリコンウェハ21
との接着界面21aから剥離することはない。Oxide film 22 formed on the silicon layer 1c 20 on the element formation side
is less than the thickness of the element forming side silicon wafer 20, so the thickness of the element forming side silicon wafer 20 is 1 μm.
Even in the case of ultra-thin film type devices, the stress generated in silicon wafers due to the difference in thermal expansion coefficients between silicon and silicon oxide can be significantly reduced compared to conventional devices. As a result, the thickness of the silicon wafer 20 on the element forming side is 1 μm.
Even in the ultra-thin film type, the element formation side silicon wafer 20 and the oxide film 22 are the supporting substrate side silicon wafer 21.
It will not peel off from the adhesive interface 21a.
第2図は本発明の一実施例を製造する:[程図を丞す。 FIG. 2 shows a process diagram for manufacturing an embodiment of the present invention.
本実施例は、薄膜化後の素子形成側シリコンウェハ10
aの厚さが0.5μmで、ウェハ面内の膜厚分布が±0
.2μmの張合わせSOI基板を製造する場合である。In this example, a silicon wafer 10 on the element forming side after thinning is used.
The thickness of a is 0.5 μm, and the film thickness distribution within the wafer plane is ±0.
.. This is a case where a 2 μm bonded SOI substrate is manufactured.
第2図<A)に丞す如く、素子形成側シリコンウェハ1
0を酸化温度1000℃9M化時間20分の条件でスチ
ーム酸化し、その表面に厚さ0.1μmの酸化膜11a
、11bを形成する。酸化膜11a、11bの厚さは薄
膜化後の素子形成側シリコンウェハ10aの厚さ未満で
あればよく、上記厚さに限定されない。次に、第2図(
B)に示す如く、支持基板側シリコンウェハ12を酸化
温度1100℃、酸化時間120分の条件でスチーム酸
化し、その表面に厚さ1μmの酸化膜13a。As shown in Fig. 2<A), the silicon wafer 1 on the element formation side
0 was steam oxidized at an oxidation temperature of 1000°C for 9M for 20 minutes, and an oxide film 11a with a thickness of 0.1 μm was formed on the surface.
, 11b. The thickness of the oxide films 11a and 11b may be less than the thickness of the element forming side silicon wafer 10a after thinning, and is not limited to the above thickness. Next, see Figure 2 (
As shown in B), the support substrate side silicon wafer 12 is steam oxidized at an oxidation temperature of 1100° C. and an oxidation time of 120 minutes to form an oxide film 13a with a thickness of 1 μm on its surface.
13bを形成する。13b is formed.
次に、第2図(C)に示す如く、素子形成側シリコンウ
ェハ10と支持基板側シリコンウェハ12とを表面どう
し重ね合わせ、1100℃、120分の条件の熱処理で
接着する。次に、研削装置で素子形成側シリコンウェハ
10を厚さ3μ園まで薄膜化しく第2図(C)の破線)
、シかる後、第2図(D)に示す如く、研磨装置で厚さ
0.5±0.2μmまで薄くし、本発明になる張合わせ
Sol基板が完成する。Next, as shown in FIG. 2C, the silicon wafer 10 on the element forming side and the silicon wafer 12 on the supporting substrate side are placed one on top of the other and bonded together by heat treatment at 1100° C. for 120 minutes. Next, the silicon wafer 10 on the element forming side is thinned to a thickness of 3 μm using a grinding machine (broken line in FIG. 2(C)).
After that, as shown in FIG. 2(D), the substrate is thinned to a thickness of 0.5±0.2 μm using a polishing device, thereby completing the bonded Sol substrate of the present invention.
このように、本発明では、素子形成側シリコンウェハ1
0aに形成された酸化膜11bのI!!厚が素子形成側
シリコンウェハ10aの膜厚未満(本実施例では115
)であるため、素子形成側シリコンウェハ10aの厚さ
を1μm未満と薄くシても、酸化シリコンとシリコンと
の熱膨張係数の違いによってシリコンウェハに生じる応
力は従来例よりも大幅に小さくでき、従って、素子形成
側シリコンウェハ10a及び酸化1!llbが受持基板
側シリコンウェハ12との接着界面(酸化膜13aの1
面〉から剥離することはない。In this way, in the present invention, the element forming side silicon wafer 1
I! of the oxide film 11b formed on 0a! ! The thickness is less than the film thickness of the element forming side silicon wafer 10a (in this example, 115
) Therefore, even if the thickness of the silicon wafer 10a on the element forming side is reduced to less than 1 μm, the stress generated in the silicon wafer due to the difference in thermal expansion coefficient between silicon oxide and silicon can be significantly reduced compared to the conventional example. Therefore, the element forming side silicon wafer 10a and the oxidation 1! llb is the adhesive interface with the silicon wafer 12 on the supporting substrate side (1 of the oxide film 13a)
It will not peel off from the surface.
なお、上記実施例は表面酸化膜を素子形成側シリコンウ
ェハ及び支持基板側シリコノウ1ハの両方に形成したも
のであるが、本発明はこれに限定されるものではなく、
素子形成側シリコンウェハのみに形成したものでもよく
、要は少なくと6素子形成側シリコンウ1ハに表面酸化
膜が形成されたものであればよい。In the above embodiment, the surface oxide film was formed on both the silicon wafer on the element forming side and the silicon wafer on the support substrate side, but the present invention is not limited to this.
It may be formed only on the silicon wafer on the element formation side, and in short, it is sufficient if the surface oxide film is formed on at least the six element formation side silicon wafers.
以上説明した如く、本発明によれば、素子形成側シリコ
ンウェハに形成された酸化膜の厚さを素子形成側シリコ
ンウェハの厚さ未満としたため、素子形成側シリコンウ
ェハの厚さが1μ量と超薄膜タイプのものでも素子形成
側シリコンウェハに発生する応力は従来例のものよりも
大幅に小さくなり、従って、素子形成側シリコンウェハ
及び酸化膜が支持基板側シリコンウェハとの接着界面か
ら剥離することを防止できる。As explained above, according to the present invention, the thickness of the oxide film formed on the silicon wafer on the element formation side is less than the thickness of the silicon wafer on the element formation side, so that the thickness of the silicon wafer on the element formation side is 1μ. Even with the ultra-thin film type, the stress generated on the silicon wafer on the element forming side is significantly smaller than that of conventional types, and therefore the silicon wafer on the element forming side and the oxide film peel off from the adhesive interface with the supporting substrate side silicon wafer. This can be prevented.
第1図は本発明の原理図、
第2図は本発明の一実施例を製造する工程図、第3図は
従来の一例の構成図である。
図において、
10は素子形成側シリコンウェハ、
108.20は薄膜化された素子形成側シリコノウ1ハ
、
11a、11b、13a、13b、22は酸化膜、12
.21は支持基板側シリコンウェハを示す。FIG. 1 is a principle diagram of the present invention, FIG. 2 is a process diagram for manufacturing an embodiment of the present invention, and FIG. 3 is a configuration diagram of a conventional example. In the figure, 10 is a silicon wafer on the element formation side, 108.20 is a thinned silicon wafer on the element formation side, 11a, 11b, 13a, 13b, 22 is an oxide film, 12
.. Reference numeral 21 indicates a silicon wafer on the support substrate side.
Claims (1)
基板側シリコンウェハ(21)との間に設けられた酸化
膜(22)は少なくとも素子形成側シリコンウェハ(2
0)の表面に形成された酸化膜であり、該素子形成側シ
リコンウェハ(20)の厚さが1μm未満に定められた
張合わせSOI基板において、 上記素子形成側シリコンウェハ(20)に形成された酸
化膜の厚さを、上記素子形成側シリコンウェハ(20)
の厚さ未満に形成してなることを特徴とする張合わせS
OI基板。[Claims] The oxide film (22) provided between the thinned element forming side silicon wafer (20) and the supporting substrate side silicon wafer (21) is at least
0), which is an oxide film formed on the surface of the element forming side silicon wafer (20) in a bonded SOI substrate in which the thickness of the element forming side silicon wafer (20) is determined to be less than 1 μm. The thickness of the oxide film formed on the silicon wafer (20) on the element forming side is
Laminated S characterized by being formed to a thickness less than
OI board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19462389A JPH0360007A (en) | 1989-07-27 | 1989-07-27 | Clad sio substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19462389A JPH0360007A (en) | 1989-07-27 | 1989-07-27 | Clad sio substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0360007A true JPH0360007A (en) | 1991-03-15 |
Family
ID=16327601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19462389A Pending JPH0360007A (en) | 1989-07-27 | 1989-07-27 | Clad sio substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0360007A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61276361A (en) * | 1985-05-31 | 1986-12-06 | Toshiba Corp | Manufacture of composite semiconductor substrate |
| JPS62174969A (en) * | 1986-01-28 | 1987-07-31 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6477951A (en) * | 1987-09-19 | 1989-03-23 | Fujitsu Ltd | Semiconductor substrate and manufacture thereof |
-
1989
- 1989-07-27 JP JP19462389A patent/JPH0360007A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61276361A (en) * | 1985-05-31 | 1986-12-06 | Toshiba Corp | Manufacture of composite semiconductor substrate |
| JPS62174969A (en) * | 1986-01-28 | 1987-07-31 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6477951A (en) * | 1987-09-19 | 1989-03-23 | Fujitsu Ltd | Semiconductor substrate and manufacture thereof |
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