JPH0360111A - Contact exposure - Google Patents

Abstract

PURPOSE:To improve the close adherence and evenness of an exposure mask and a photoresist layer for increasing the resolving degree of the pattern exposure by a method wherein recessed parts are provided on the dead parts of a substrate surface to be coated with the photoresist layer. CONSTITUTION:When recessed parts 14 are formed in the coating surface of a photoresist layer 11, even if the said coating surface especially the actually effective regions such as circuit element formation part or wiring formation parts, etc., to be pattern-exposed are taken in a flat planar shape, the marginal resolving degree therein can be decreased to increase the resolving degree. That is because any distortion, etc., on the surface layer of a substrate 13 e.g. a semiconductor wafer can be absorbed by existing recessed parts 14 to eliminate any warping of the substrate 13 for providing it with excellent flatness furthermore, any air creeping in the gap between the photoresist layer 11 and an exposure mask 12 thereon closely adhered to each other can be vented through the recessed parts 14 thereby avoiding the impediment to the close adherence by the existing air vesicles.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to pattern exposure of a photoresist in photolithography technology applied in the manufacturing process of various semiconductor devices, and in particular to a contact exposure method.

[Summary of the invention]

In the contact exposure method in which an exposure masker is placed in close contact with a photoresist layer and pattern exposure is performed on the photoresist layer, the present invention provides an exposure mask by providing a recess in an ineffective portion of a substrate surface to which a photoresist layer is applied. The aim is to improve the adhesion and uniformity of the photoresist layer and the resolution of pattern exposure.

[Conventional technology]

Photolithography is often applied in various microfabrication processes, such as the manufacturing process of semiconductor devices.

For example, as a circuit element in a semiconductor integrated circuit, a field effect transistor, such as a high electron mobility field effect transistor using a two-dimensional electron gas channel, uses a semi-insulating substrate (1
) For example, on a semi-insulating GaAs substrate, a channel layer (3) is formed on the undoped GaAs layer (3), for example, 5000 nm thick, through a buffer layer (2) of a superlattice structure, 2000 nm thick, for example. A semiconductor substrate (5), ie, a semiconductor wafer, is provided, on which a GaMAs layer of, for example, 700 A as a barrier layer (4) is epitaxially grown in sequence, and this barrier layer (4) and channel layer (3) are further epitaxially grown. Mesa etching is performed to form mesa a (6) across the buffer layer (2), and ohmic electrodes (7s) and (7d) of the source and drain are formed on the mesa separated from the others by the mesa groove (6). ) and a gate electrode (7g>) is formed between them.

In such semiconductor integrated circuits, the formation of mesa grooves (6) provides isolation between elements, that is, isolation between each circuit element, in this example a high electron mobility field effect transistor. Forming the mesa groove (6) involves each step after the formation of the mesa groove (6).
For example, in various types of photolithography for forming wiring patterns, opening contact windows in interlayer insulating layers, or forming pattern wiring on top of them, exposure is performed based on the difference in exposure amount between the mesa top and the inside of the mesa groove (6). Due to the difficulty of the conditions, this mesa top and mesa groove (6)
There are many disadvantages such as hindering the formation of high-precision fine patterns due to differences in exposure conditions within the process, and lowering reliability due to breakage of the formed wiring pattern.

For this reason, even in this type of semiconductor integrated circuit, there is a tendency to adopt a method of avoiding separation between elements (that is, isolation) by mesa grooves and creating a Brenner type structure with a flat surface.

On the other hand, pattern exposure of a photoresist in photolithography in the manufacturing process of semiconductor devices can be roughly divided into a step-type reduction projection exposure method and a contact-type exposure method. In the reduction projection exposure method, the reticle of the exposure pattern is moved in steps relative to the exposed photoresist surface to sequentially expose micropatterns, whereas in the contact exposure method, the photoresist layer is The photoresist layer is exposed to pattern light according to the optical pattern formed by the light-transmitting areas and the light-transmitting areas on the exposure mask by placing an exposure mask in close contact with the photoresist layer and irradiating it with, for example, so-called deep ultraviolet rays. .

The latter contact exposure method has the advantage that the design of the optical system is easy because the patterns of the exposure mask and the exposed area are 1:1.

By the way, the minimum exposure dimension, that is, the critical resolution in pattern exposure, if the resolution of the photoresist itself is ignored, is based on the Fresnel diffraction theory: resolution R=C86-7<where C is a constant, λ is the wavelength of the light source, and g is the distance between the exposed surface of the photoresist and the mask. ) Since the wavelength of the light source is usually constant depending on the device, the contribution of this wavelength λ to the resolution is constant. however,
The interval length g changes depending on various conditions of the exposure process, such as the semiconductor device manufacturing process. For example, when surface layers such as various insulating layers are deposited on a substrate, stress is generated due to this and the substrate is warped, and the surface of the photoresist layer formed thereon and the exposure mask The adhesion between the two surfaces is inhibited, resulting in a region where a gap is generated, resulting in a partial reduction in resolution in this region.

On the other hand, in the manufacturing process τ of a semiconductor integrated circuit having a mesa-type circuit element as explained in FIG. FIG. 5 shows the results of measuring the relationship between time and resolution. In this case, the width of the gate electrode (7g), that is, the gate length Lg = 0.6 μm
In this case, the curves (51), (52), and (53) respectively represent the depth Dp of the mesa groove (6), and the depth Dp = 8oo
People, Dp=115OA, Dp=4500 people.

When Dρ=gooo person, there is still another curve〈54)
(54) and (51) to (53) show that each limit resolution point is indicated by an X mark. As shown, as the mesa groove (6) becomes deeper, the limit resolution becomes smaller and the resolution improves.

Therefore, when applying planar structure isolation technology to a semiconductor integrated circuit by avoiding isolation due to the mesa groove (6) as described above, there is a limit as shown by the curve (54) in FIG. A problem arises in that the resolution deteriorates.

[Problem to be solved by the invention]

An object of the present invention is to prevent deterioration of the critical resolution even when the substrate surface to which the photoresist layer is adhered is flat in the contact exposure method.

[Means to solve the problem]

In the present invention, as shown in FIG. A recess (14) is formed in an ineffective portion of the surface of the substrate (13) to which the etchant is applied, such as a semiconductor wafer surface, such as a scribe line or an area surrounded by the scribe line where no circuit elements or the like are formed.

[Effect]

In the case of the method of the present invention described above, that is, when the recess (14) is formed on the adhered surface of the photoresist layer (11>),
As shown by curve (31) in FIG. 3, the surface to which this photoresist layer <11> is adhered, especially the actual effective area such as the circuit element formation area or its wiring formation area where pattern exposure is performed, is a flat planar surface. Even though it is a type, we were able to lower its limiting resolution. In other words, we were able to improve the resolution.

This is because the distortion caused by the surface layer such as an insulating layer formed on the substrate (13), such as a semiconductor wafer, is absorbed by the presence of the recess (14), and the warpage of the substrate is eliminated, resulting in excellent flatness. Furthermore, when the exposure mask (12) is in close contact with the photoresist layer (11), the air (bubbles) that enters between them escapes into the recess (14) and the presence of these bubbles. This seems to be due to the fact that the adhesion is prevented from being inhibited by this.

〔Example〕

An example of the present invention will be described in detail with reference to FIG.

In this example, as shown in FIG. 1A, an SlO□
This is intended to perform pattern exposure on a photoresist when performing required pattern processing by photolithography on an insulating layer (15) such as the above.

In this case, as shown in FIG. 1B, on the surface of the substrate (13) on which the photoresist layer is to be deposited, as shown in FIG. 1B,
For example, if the depth Dp of the invalid part on the base body (13) is Dp =
A recess (14) of 5,000 to 1 μm is formed by IJ lithography. In this case, the semiconductor substrate (
Semiconductor wafer) (13) In a semiconductor wafer, a large number of integrated circuit parts, for example, are simultaneously arranged vertically and horizontally like the eyes of a substrate, and are finally separated between each integrated circuit part and made into chips. As shown in Figure 2, scribe line parts (17) with a width of more than 100 μm are provided in a grid pattern between the forming parts (16) of semiconductor devices such as integrated circuits to separate them. The formation position of the recessed portion (14) is the scribe line portion (17) where the semiconductor device is not actually formed.
Furthermore, even within the forming portion (16) of the semiconductor device, each invalid portion is defined as an invalid portion where no circuit element wiring or the like is actually formed.

This recessed portion (14) is a scribe line portion (14).
7) Above, the width can be selected to be about 100 μm. Also,
Since the formation of this concave portion (14) does not require particularly high precision, it is possible to form the substrate (13) by a normal contact exposure method.
There is no problem even if there is warpage or the like. After that, the entire surface was coated with, for example, Hitachi Chemical's negative resist RD200O.
Apply a photoresist layer (11) of N2.

Next, the 1st rI! As shown in JC, a desired optical pattern (12p) is formed in close contact with this photoresist layer <11>.
) with an exposure mask (12>) closely placed thereon, and exposure by deep ultraviolet irradiation is performed through this.

Thereafter, as shown in the first diagram, the exposure mask (12) is removed, and the photoresist layer (11) is developed to pattern the photoresist layer (11).

This patterned photoresist layer (11
) as an etching resist, for example, an insulating layer (
15) Perform etching.

In the above-mentioned example, the present invention is applied when forming an etching resist for the insulating layer (15), but it can also be used as an etching mask or an ion implantation mask for various wiring or the substrate (11). The present invention can be applied to patterning a resist.

〔Effect of the invention〕

As described above, in the present invention, the recess (1
By providing 4), it is possible to improve the resolution in the contact exposure method, so it is possible to achieve finer patterns even when a semiconductor integrated circuit is made into a planar type, for example, without having a mesa type configuration. This brings significant practical benefits, such as improved reliability through Brenner formation, the formation of finer patterns, and the ability to manufacture higher-density integrated circuits.

[Brief explanation of drawings]

Figure 1 is an enlarged cross-sectional view of each step to explain the method of the present invention, Figure 2 is a plane pattern diagram of the concave portion, and Figures 3 and 5 are measurement curve diagrams showing the relationship between exposure time and resolution. ,
FIG. 4 is an enlarged cross-sectional view of an example of a semiconductor integrated circuit for explaining the present invention. (13) is the base body, (14> is the recessed part, (11) is the photoresist layer, and (12) is the exposure mask. Agent Hidemori Matsukuma Koubei '15/ll Master -> Figure 2 Procedural amendment form January 17, 1990

Claims (1)

[Claims] In a contact exposure method in which the photoresist layer is exposed to pattern light by bringing an exposure mask into close contact with the photoresist layer, a recess is provided in an ineffective portion of the substrate surface to which the photoresist layer is applied. A contact exposure method characterized by: