JPH036311U

JPH036311U -

Info

Publication number: JPH036311U
Application number: JP6647589U
Authority: JP
Priority date: 1989-06-07
Filing date: 1989-06-07
Publication date: 1991-01-22

Description

[Brief explanation of drawings]

第１図は本考案に係る任意波形発生装置の一実
施例を示す構成図、第２図はその動作を説明する
ための図、第３図は従来の任意波形発生装置の構
成図、第４図は遅延部の構成図である。１……アドレス発生部、２……第１の波形メモ
リ、３……第２の波形メモリ、５……第１のＤＡ
変換部、６……第２のＤＡ変換部、７，８……ア
ナログ回路、２０……演算部。 FIG. 1 is a block diagram showing an embodiment of an arbitrary waveform generator according to the present invention, FIG. 2 is a diagram for explaining its operation, FIG. 3 is a block diagram of a conventional arbitrary waveform generator, and FIG. The figure is a configuration diagram of the delay section. DESCRIPTION OF SYMBOLS 1... Address generation part, 2... First waveform memory, 3... Second waveform memory, 5... First DA
Conversion section, 6... Second DA conversion section, 7, 8... Analog circuit, 20... Arithmetic section.

Claims

[Claims for Utility Model Registration] An address generation unit that generates an address signal; a second waveform memory in which waveform data is stored and into which the output address of the address generation unit is input as an address signal; and the second waveform a second digital-to-analog conversion section that converts the output of the memory into an analog signal; a calculation section that receives the output of the address generation section and a predetermined value and calculates a delayed address signal from these values; and a calculation section that calculates a delayed address signal from these values; an arbitrary waveform generator comprising: a first waveform memory in which the output of the arithmetic unit is stored and inputted as an address signal; and a first digital-to-analog conversion unit that converts the output of the first waveform memory into an analog signal. .