JPH0375683U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of this invention. FIG. 2 is an open loop gain characteristic diagram in one embodiment of this invention. FIG. 3 is a block diagram showing the configuration of a conventional example. FIG. 4 is an open loop gain characteristic diagram in a conventional example. 1 and 2... variable delay line, 3... horizontal synchronization separation circuit, 5... burst gate, 6 and 7... horizontal synchronization signal phase comparator and color burst signal phase comparator, 8 ₁ and 8 ₂ ... voltage controlled oscillator, 9 ₁ and 9 ₂ ...phase correction amplifier.

Claims (1)

[Scope of utility model registration request] First and second variable delay elements connected in cascade and to which a reproduced video signal is input; a first voltage-controlled oscillator that supplies an operating clock signal to the first variable delay element; a second voltage controlled oscillator that supplies a clock signal; a first phase comparison means that compares the phase of the horizontal synchronization signal extracted from the output of the first variable delay element with a reference horizontal synchronization signal; A first voltage controlled oscillator is provided with a second phase comparison means for phase comparing the extracted color burst signal and a reference color burst signal, and uses a voltage accompanying the phase comparison output from the first phase comparison means as an oscillation frequency control voltage. A time base correction circuit characterized in that the voltage associated with the phase comparison output from the second phase comparison means is supplied to the second voltage controlled oscillator as an oscillation frequency control voltage.