JPH0418458U - - Google Patents

Info

Publication number
JPH0418458U
JPH0418458U JP1990060361U JP6036190U JPH0418458U JP H0418458 U JPH0418458 U JP H0418458U JP 1990060361 U JP1990060361 U JP 1990060361U JP 6036190 U JP6036190 U JP 6036190U JP H0418458 U JPH0418458 U JP H0418458U
Authority
JP
Japan
Prior art keywords
lead
land
lead frame
wire
perforation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990060361U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990060361U priority Critical patent/JPH0418458U/ja
Publication of JPH0418458U publication Critical patent/JPH0418458U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案に係る第１の実施例を示す斜視
図、第２図は同じく断面図、第３図は本考案に係
る第２の実施例を示す斜視図、第４図は同じく断
面図である。第５図は従来のハイブリツドＩＣの
斜視図、第６図は従来の半導体装置の斜視図、第
７図は従来の半導体装置をプリント基板に実装し
た際の断面図である。 ９……リードフレーム、１０……ランド部、１
１……半導体ペレツト、１２……リード、１３…
…ワイヤ、２０……所定のリード、４０……絶縁
板、４１……穿孔部。

Claims (1)

  1. 【実用新案登録請求の範囲】 ２枚のリードフレームの各ランド部にマウント
    した半導体ペレツトと各ランド部近傍に配置した
    リードとをワイヤにて接続し、各リードフレーム
    の裏面を絶縁板を介して対向させた半導体装置に
    おいて、 上記絶縁板のランド部とリードの基端部との間
    に穿孔部を設け、一方のリードフレーム上の半導
    体ペレツトと他のリードフレームのリードとを上
    記穿孔部を介してワイヤにて接続したことを特徴
    とする半導体装置。
JP1990060361U 1990-06-06 1990-06-06 Pending JPH0418458U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990060361U JPH0418458U (ja) 1990-06-06 1990-06-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990060361U JPH0418458U (ja) 1990-06-06 1990-06-06

Publications (1)

Publication Number Publication Date
JPH0418458U true JPH0418458U (ja) 1992-02-17

Family

ID=31587662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990060361U Pending JPH0418458U (ja) 1990-06-06 1990-06-06

Country Status (1)

Country Link
JP (1) JPH0418458U (ja)

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