JPH0425952A - Address distribution circuit - Google Patents

Abstract

PURPOSE:To facilitate execution by controlling reading from a shared memory by means of a signal obtained by means of wired ORing the self address detection signal of address decoding circuits in I/O and a local memory. CONSTITUTION:For reading data from I/O 5 or the local memory 6, either self address detection signal 11 or 12 is turned on and a wired signal 13 obtained by wired-Oring the signal by an OR circuit 10 is turned on(becomes 'true'). When the wired OR signal 13 is turned on, a data input/output gate circuit 9 in the shared memory 2 closes an output gate for a data bus 4 from the shared memory 2 and prevents that the signal from the shared memory 2 collides with the signal from I/O 5 or the local memory 6 on the data bus 4. Thus, a micro processor system whose constitution is simple and whose extendability is high can be obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an address distribution circuit in a microprocessor system, and in particular, the present invention relates to an address distribution circuit in a microprocessor system, and in particular, to distribution of memory specified areas of shared memory, various ■/○, and local memories in a limited memory space. This invention relates to an address distribution circuit in a system.

[Conventional technology]

Conventionally, an exemplary microprocessor system includes a microprocessor, a shared memory, an input/output device with Ilo, a local memory, and a mapping memory, each coupled by an address bus and a data bus. was. The address distribution circuit in this type of microprocessor system stores in advance the classification of each address in the mapping memory as a shared memory area or another area. The shared memory is controlled by an address distribution circuit so as to permit access to its own memory only when the output of the mapping memory is determined to be a shared memory area.

[Problem to be solved by the invention]

However, such address distribution circuits have the disadvantage that it is difficult to arbitrarily divide the address space because the finer the division of the address space in the mapping memory, the larger the capacity of the mapping memory. . Furthermore, when changing the division of the address space, the program executed by the microprocessor must be changed, not only when the mapping memory is a ROM but also when the memory is rewritable by the microprocessor. There was also the drawback that it was not.

[Means to solve the problem]

The address distribution circuit of the present invention is a microprocessor system in which a microprocessor, a shared memory, and one or more circuits whose addresses are mapped onto the memory space of the shared memory are interconnected by an address bus and a data bus. In the address distribution circuit, an OR circuit performs a wired OR of self-address detection signals detected by each address decoding circuit in the circuit, and the shared memory is designated for memory reading by an address in a memory space of the shared memory, and and a data input/output gate circuit provided in the shared memory that prohibits outputting read data of the shared memory to the data bus when the wired OR signal is "true".

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a diagram showing how the address space of the shared memory is distributed in the embodiment.

The microprocessor system shown in FIG. 1 has a microprocessor 1 and a shared memory 2.
The address was mapped onto the memory space of l10
input/output equipment (not shown) with 5 and local memory 6
have. These components are connected by an address bus 3 and a data bus 4. In FIG. 2, a part of the shared memory area 21 in the shared memory 2 is l1
05 and local memory 6 are allocated to an I10 designated area 22 and a local memory designated area 23.

An address distribution circuit that distributes the address space of the shared memory 2 in this manner will be described below. The address decoding circuit 7 in the l105 decodes only the address addressed to itself among the addresses of write or read requests sent from the microprocessor 1 to the address bus 3. If an address addressed to itself is detected, it sends a self-address detection signal 11 indicating this to the OR circuit 10. A wired OR signal 13 that has been wired ORed by the OR circuit 10 is input to a data input/output gate circuit 9 in the shared memory 2 . Address decode circuit 8 in local memory 6 similarly sends own address detection signal 12 to OR circuit 10 when it detects an address addressed to itself.

When reading from T105 or the local memory 6, either the own address detection signal 11 or 12 turns ON, and the wired signal 13 obtained by wire-ORing by the OR circuit 10 becomes 0N (r true J). become.

The data input/output gate circuit 9 in the shared memory 2 closes the output gate from the shared memory 2 to the data bus 4 when the wired OR signal 13 is ON, and connects the signal from the shared memory 2 and T105 or T105 on the data bus 4. local memory 6
This prevents the signals from colliding with each other.

Through the operations described above, the address decoding circuit 7 or 8 of the l105 or local memory 6 determines the address. 11 in any address space location and area of shared memory 2
05 and local memory 6 can be allocated.

Note that when writing to 1105 or the local memory 6, there is no need to prohibit writing to the shared memory 2 at the same time. Therefore, the wired OR signal 13
Even if the input/output gate circuit 9 is turned on, the input gate of the input/output gate circuit 9 does not need to be closed.

In this way, if reading from the shared memory 2 is controlled by the wired OR signal generated by the own address detection signal of each device (circuit) whose address is mapped on the memory space of the shared memory 2, the microprocessor system The scalability of is also increased. For example, newly l1
014 into this system, I 1014
Connect 11014 to address bus 3 and data bus 4,
By simply connecting the own address detection signal 16 sent by the address decoding circuit 15 in the internal address decoding circuit 15 to the OR circuit 10, the address of I1014 can be placed at the position of the I10 specified area 24 shown in FIG. 2, and the previous system is completely changed. There is no need to add

〔Effect of the invention〕

As explained above, the present invention eliminates the mapping memory, and controls reading from the shared memory by a signal obtained by wire-ORing the own address detection signal of the address decoding circuit of each l1010-cal memory. As a result, it becomes possible to allocate the addresses of Ilo or local memory to any address space location and area of the shared memory determined by the address decoding circuit of each Ilo or local memory. In addition, even when adding a circuit block with Ilo, address distribution can be changed automatically by simply physically connecting the circuit block to the bus.As explained above, this address distribution circuit is used. This has the effect of providing a microprocessor system that is easy to configure and highly expandable.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a diagram showing how address space is distributed in the embodiment. 1... Microprocessor, 2... Shared memory, 3
...Address bus, 4...Data bus, 5,14.
...Ilo, 6... Local memory, 7, 8.15.
... Address decoding circuit, 9... Data input/output gate circuit, 10... OR circuit, 11, 12, 16...
Own address detection signal, 13... wired OR signal,
21 shared memory area, 4... I 10 designated area, 23... local memory designated area.

Claims (1)

[Claims] An address distribution circuit for a microprocessor system in which a microprocessor, a shared memory, and one or more circuits whose addresses are mapped onto the memory space of the shared memory are interconnected by an address bus and a data bus, wherein the circuit Wired O of own address detection signal detected by each address decoding circuit in
an OR circuit that takes R, and outputting read data of the shared memory to the data bus when the shared memory is designated for memory reading by an address of the memory space of the shared memory and the wired OR signal is "true". and a data input/output gate circuit provided in the shared memory for inhibiting data input/output gate circuits.