JPH0438545A - Memory protecting circuit - Google Patents

Abstract

PURPOSE:To identify generated error information in the stage of an error processing in terms of a program by storing a generated data signal and an illegal address into a memory address when address error occurs. CONSTITUTION:When an address error signal (2) is made significant, a write signal generating circuit 17 for illegal address storage generates a write signal for illegal address storage, and a selector circuit selects a delay address signal (12), illegal address storing write signal and address signal for illegal address storage as a write data signal, write signal and write address signal. Then, the generated illegal address is stored in the address for illegal address storage. Thus, the state of occurrence of the address error can be identified in the stage of the error processing in terms of a program.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention stores, when an address error occurs during memory write, the invalid address at that time as data in the set invalid address storage address (by doing so, The present invention relates to a memory protection circuit that can identify the state of address error occurrence during error processing.

[Prior Art] FIG. 4 is a block diagram showing a conventional memory protection circuit. In the figure, (1) is an oscillation circuit, (2) is an address error signal, and (3) is a device that detects whether an address error has occurred during memory write, and if an address error occurs, an address error signal (2). Invalid address detection circuit that makes significant, (4) is memory, (5) is address signal, (6) is data signal, (7) is write signal, (8
) outputs an address signal (5), a data signal (6) and a write signal (7), and when the address error signal (2) becomes significant, the central processing unit (9) starts error processing.
) if an address error occurs during memory write,
Set the save address to store the data to be written at that time (save address storage register, (10)
is the memory address for storing data, and when the address error signal (2) is not significant, the central processing unit (8)
Select the address signal (5) output from .

When the address error signal (2) is significant, the selector circuit selects the save address set in the save address storage register (9). (11) is the address error signal (2) is the selector circuit that selects the save address set in the save address storage register (9). (
A delay circuit delays the address signal (5) from reaching the selector circuit (10) so that the address signal (5) reaches the selector circuit (10).

(12) is the delayed address signal delayed by the delay circuit (11), (13) is the delayed data signal delayed by the delay circuit (11), and 114 is the delayed address signal delayed by the delay circuit (11).
), (15) is an evacuation address signal that outputs the evacuation address set in the evacuation address storage register (9), (161 is a selector address signal that outputs the address selected by the selector circuit (10), (27) is the oscillation circuit (1)
This is the clock signal output from the .

FIG. 5 is a timing chart of a conventional memory protection circuit. First, an address signal (5) is output at tl. After the address signal (5) is determined, the data signal (
6) and the write signal (7) are output at the same timing t2. Detection of whether an address error has occurred is performed at the midpoint of the pulse width of the write signal (7) t"2, t'?・
It will be held in... In this example, the delay circuit (11) operates to delay the input signal by one clock. Therefore,
Data writing is performed at the rising edge t4, t9, etc. of the delayed write signal (14).

No address error occurs in the memory write cycle of T1. At this time, the memory write is executed at the rising edge t4 of the delayed write signal (14), and then the fifth process is started.

The memory write cycle T2 represents a case where an address error occurs. When an address error is detected by the invalid address detection circuit (3) at t'7, the address error signal (2) becomes significant.

The selector circuit (10) is a save address storage register (
9) Select the save address signal (15). Therefore, the save address signal (15) is output to the selector address signal 6) from t"7, and data is written to the save address at the rising edge t9 of the delayed write signal (14). The central processing unit (8) detects an address error. When signal (2) becomes significant, the next process is stopped and error handling is executed.

[Problems to be Solved by the Invention] As described above, in the conventional memory protection circuit, when the central processing unit (8) stops due to the occurrence of an address error,
Although data at the time of an address error is protected, an invalid address that has occurred is not protected, so there is a problem in that the state of address error occurrence cannot be identified in error processing.

This invention was made to solve this problem, and when the address error signal (2) becomes significant,
The address for storing an invalid address that has been set in advance in the address register for storing an invalid address (By writing the invalid address that has occurred, it is possible to programmatically identify the state of address error occurrence at the error processing stage. The purpose is to

[Means for Solving the Problems] The memory protection circuit according to the present invention has an address error signal (2) that is insignificant corresponding to each of the write data signal, write write signal, and write address signal output to the memory (4). When is the delayed data signal (13)
, delayed write signal (14) and delayed address signal (1
2), and when the address error signal (2) is significant, a delayed address signal (12), a write signal for storing an invalid address, and an address signal for storing an invalid address, and a memory for storing the invalid address. The address is set (an address register for storing an invalid address is provided, and a write signal generation circuit for storing an invalid address is provided to generate a write signal for writing the invalid address to the memory address set in the address register for storing an invalid address. , when an address error occurs, the incorrect address that has occurred is stored in the memory (4).

[Operation] In the memory protection circuit according to the present invention, when the address error signal (2) becomes significant, the write signal generation circuit for storing an invalid address generates a write signal for storing an invalid address, and the selector circuit generates a write data signal and a write write signal. The delayed address signal (121), the write signal for storing an invalid address, and the address signal for storing an invalid address are selected as the signal and the write address signal so that the generated invalid address can be stored in the address for storing the invalid address.

[Example] FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, (17) is the address error signal (2
) is present or absent, a write signal generation circuit for storing an invalid address generates a write signal for writing an invalid address to the memory (4), and (18) is a write signal generation circuit for storing an invalid address in which a memory address to store the invalid address is set. Address register, (191 is a write signal for storing an invalid address, (20) is an address signal for storing an invalid address, +211 is a write data signal that gives data to be written to the memory (4).

(22) is a write write signal that gives an instruction to write to memory (4), (231 is a write address signal that gives an address to write to memory (4), (24)
is the write data signal (211, the write write signal (
22) and the write address signal (23), when the address error signal (2) is not significant,
It outputs the delayed data signal f13), the delayed write signal (14), and the delayed address signal (12) (hereinafter referred to as 1 normal mode), and when the address error signal (2) is significant, the delayed address signal (12) is output. , a selector circuit that outputs a write signal for storing an invalid address (19) and an address signal for storing an invalid address (201 (hereinafter referred to as an invalid address mode)).

(25) is a delay circuit that delays the operation of the selector circuit (24) so that when an address error occurs, the data at that time is written to the save address and then stored as data at an invalid address. +26) is delayed by the delay circuit (25). This is a delayed address error signal.

FIG. 2 is a timing chart when no address error occurs, and FIG. 3 is a timing chart when an address error occurs.

The operation of the circuit when no address error occurs will be explained with reference to FIG.

Address signal (5) output from the central processing unit (8)
is delayed by a delay circuit (11) and output as a delayed address signal (2) at timing t1.

Since the address error signal (2) is not significant, the selector address signal (16) and the delayed address signal (2) become the same at the same timing t1. Selector circuit (24)
Since the normal mode is selected, the write address signal (23) is supplied with the delayed address signal (1) at timing t1.
2) is output via the selector circuit (10) and the selector circuit (24). Similarly, the write data signal (2
1) and write write signal (22) at timing t3.
Delayed data signal (13) and delayed write signal (14)
is output. The memory (4) has a write write signal (
At the rising edge t5 of 22), the write address signal (
23) That is, the write data signal (21), that is, the data of the delayed data signal (13), is written to the address of the delayed address signal (12).

Next, the operation of the circuit when an address error occurs will be explained with reference to FIG. As in the case where no address error occurs in Figure 2, the delayed address signal (12) is selected and output as the selector address signal (16) at tl, but the address error signal (2) is significant at +j2. Therefore, the selector address signal (16) is switched to the save address signal (15) by the selector circuit (lO). The switching of the selector circuit (24) is set at t6 with a delay of two clocks from the significant change point t2 of the address error signal (2) by the delay circuit (25). Therefore, the delayed address error signal (26) becomes significant and the normal mode is switched to the illegal address mode.
Up to 6, a delayed data signal (13) and a delayed write signal (14) are output as a write data signal (21) and a write write signal (22), respectively. At the rising edge t5 of the write write signal (22), the write data signal (21), that is, the delayed data signal (13), is written to the memory address indicated by the write address signal (23), that is, the save address signal (15). When the delayed address error signal (26) becomes significant at t6 and the selector circuit (24) switches from the normal mode to the illegal address mode, the output to the write data signal (21) is changed from the delayed data signal (13) to the delayed address. Signal (1
Switch to 2). The write address signal (23) switches from the save address signal (15) to the address signal for storing an invalid address (20). The write signal generation circuit (17) for storing an invalid address is an address error signal (
2) becomes significant, the write signal for storing an invalid address (
19) and generate 1? Output with .

t6 switched from normal mode to illegal address mode
Since the write signal for storing an invalid address (19) is selected as the write write signal (22), at the rising edge t9 of the write write signal (22), the delayed address signal output as the write data signal (21) (12) is written to the memory address set by the write address signal (23), that is, the address signal for storing an invalid address (20).

Therefore, the memory (4) has the central processing unit (8) at t5.
The data signal (6) output from the save address signal (
It is written to the save address set in step 15).

At t9, the invalid address on the address signal (15) output from the central processing unit (8) is written to the invalid address storage address set in the invalid address storage address register (18).

[Effects of the Invention] As explained above, in this invention, when an address error occurs during memory write, the generated data signal and invalid address are stored in advance in a save address storage register (9).
) and stored in the memory address set in the address register for storing invalid addresses (18), the effect is that error information that has occurred can be identified programmatically at the error processing stage of the central processing unit. be.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a timing chart when an address error does not occur in the first embodiment, and Fig. 3 shows an address error in the first embodiment. FIG. 4 is a block diagram showing a conventional example, and FIG. 5 is a timing chart of the conventional example. In the figure, (1) is an oscillation circuit, (2)
is an address error signal, and (3) is an invalid address detection circuit. (4) is memory, (5) is address signal, (6) is data signal, (7) is write signal, (8) is central processing unit,
(9) is a save address storage register, (10) is a selector circuit, (11) is a delay circuit, (121 is a delayed address signal, (13) is a delayed data signal,
(14) is a delayed write signal, (15) is a save address signal, (16) is a selector address signal,
(17) is a write signal generation circuit for storing an invalid address;
(181 is an address register for storing invalid addresses,
(19) is a write signal for storing an invalid address, f2
0) is an address signal for storing an invalid address, f21+
is the write data signal. (22) is a write write signal, (23) is a write address signal, (241 is a selector circuit, (
25) is a delay circuit, and (26) is a delayed address error signal. (27) is a clock signal. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] If an address error occurs when writing data from the central processing unit to memory, there is an address register for storing the invalid address that sets the memory address to store the invalid address, and a write signal for writing the invalid address to the memory. A write signal generation circuit for storing an invalid address to be generated, a save address storage register indicating a memory address to store data, and a memory address and data to be written are output from the central processing unit when no address error occurs. When an address error occurs, the invalid address is stored as data in the invalid address storage address set in the invalid address storage address register, and the save address set in the save address storage register is executed. 1. A memory protection circuit comprising: a selector circuit that selects data output from a central processing unit to be stored;