JPH0440563U - - Google Patents

Info

Publication number
JPH0440563U
JPH0440563U JP8137090U JP8137090U JPH0440563U JP H0440563 U JPH0440563 U JP H0440563U JP 8137090 U JP8137090 U JP 8137090U JP 8137090 U JP8137090 U JP 8137090U JP H0440563 U JPH0440563 U JP H0440563U
Authority
JP
Japan
Prior art keywords
sides
board
conductive spacer
boards
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8137090U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8137090U priority Critical patent/JPH0440563U/ja
Publication of JPH0440563U publication Critical patent/JPH0440563U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Combinations Of Printed Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はこの考案の一実施例を示す
図であり第1図はスペーサの取付方法を示す図、
第2図は複数基板の組立方法を示す図、第3図及
び第4図は従来の基板組立例であり第3図はスペ
ーサの取付方法を示す図、第4図は複数基板の組
立方法を示す図である。 1は基板、2は絶縁型スペーサ、3は貫通ボル
ト、6はベース、10は電源パターン、11はグ
ランドパターン、12は導電性スペーサ。なお、
図中、同一符号は同一、又は相当部分を示す。
1 and 2 are diagrams showing an embodiment of this invention, and FIG. 1 is a diagram showing a method of attaching a spacer,
Figure 2 shows how to assemble multiple boards, Figures 3 and 4 show examples of conventional board assembly, Figure 3 shows how to attach spacers, and Figure 4 shows how to assemble multiple boards. FIG. 1 is a substrate, 2 is an insulated spacer, 3 is a through bolt, 6 is a base, 10 is a power supply pattern, 11 is a ground pattern, and 12 is a conductive spacer. In addition,
In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のIC、抵抗、コンデンサなどの電気部品
を実装し、一つの辺を第一辺、これと直角に位置
する二つの辺を第二辺及び第四辺、第一辺と並行
に相対する方向に位置する辺を第三辺とし、第一
辺と第三辺の各縁の基板両面に電源及びグランド
用のパターン面を配置した基板、各基板を同一番
号の辺が同一方向になるようにスタツク的に重ね
て、第一、第二、第三、第四の順に基板番号を付
し、第一の基板と第二の基板、第二の基板と第三
の基板、第三の基板と第四の基板の電源パターン
及びグランドパターンを電気的に接続させるよう
に各々の基板の間に配置される導電性スペーサ、
複数の基板と複数の導電性スペーサを交互に重ね
合わせた後にこれを一括して結合する貫通ボルト
、貫通ボルトの先端ネジ部を固定するナツトより
構成され、スタツクの組み立てが導電性スペーサ
、基板、導電性スペーサ、基板、導電性スペーサ
の順番にし、貫通ボルトを上記の導電性スペーサ
側より順番に貫通させ、反対側の最端に位置する
ナツトに貫通ボルトを締め込んで、複数の基板の
電源とグランドを導電性スペーサを用いて電気的
に接続してあることを特徴とする基板。
Electrical components such as multiple ICs, resistors, capacitors, etc. are mounted, one side is the first side, the two sides located at right angles to this are the second and fourth sides, and the direction facing parallel to the first side. The side located at is the third side, and the power and ground pattern surfaces are arranged on both sides of the board on each edge of the first and third sides, and each board is arranged so that the sides with the same number are in the same direction. The boards are stacked one on top of the other, numbered in the order of first, second, third, and fourth, and the first and second boards, the second and third boards, and the third board. a conductive spacer arranged between each substrate so as to electrically connect the power supply pattern and the ground pattern of the fourth substrate;
The stack consists of a through-bolt that connects multiple substrates and conductive spacers together after they are stacked alternately, and a nut that fixes the threaded end of the through-bolt. Connect the conductive spacer, the board, and the conductive spacer in this order, pass the through bolts through them in order from the above conductive spacer side, and tighten the through bolts into the nut located at the farthest end on the opposite side to connect the power supply to multiple boards. A board characterized in that a ground and a ground are electrically connected using a conductive spacer.
JP8137090U 1990-07-31 1990-07-31 Pending JPH0440563U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8137090U JPH0440563U (en) 1990-07-31 1990-07-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8137090U JPH0440563U (en) 1990-07-31 1990-07-31

Publications (1)

Publication Number Publication Date
JPH0440563U true JPH0440563U (en) 1992-04-07

Family

ID=31627258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8137090U Pending JPH0440563U (en) 1990-07-31 1990-07-31

Country Status (1)

Country Link
JP (1) JPH0440563U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018022788A (en) * 2016-08-04 2018-02-08 Necスペーステクノロジー株式会社 Printed board connection structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018022788A (en) * 2016-08-04 2018-02-08 Necスペーステクノロジー株式会社 Printed board connection structure

Similar Documents

Publication Publication Date Title
JPH0720849Y2 (en) Busbar interconnection structure
JPH0451170U (en)
JPS63101467U (en)
JPH0440563U (en)
JPH0451171U (en)
JPH0127267Y2 (en)
JPH0451490Y2 (en)
JPH04135185U (en) cylindrical connector
JPS61183589U (en)
JPH0234859Y2 (en)
JPH0357058Y2 (en)
JPS5950447U (en) Stack of semiconductor conversion equipment
JPH0451168U (en)
JPS6342551Y2 (en)
JPS62128691U (en)
JPH0219993Y2 (en)
JPS6339960U (en)
JPH0440558U (en)
JPH0463173U (en)
JPS63136381U (en)
JPS62126847U (en)
JPS6248117U (en)
JPS58149024U (en) power bus
JPS5841920U (en) power bar
JPS6422092U (en)