JPH0442797Y2 - - Google Patents

Description

[Detailed explanation of the idea]

(a) Industrial Application Field The present invention relates to an alarm clock with a lifting device that is hung from the ceiling and lowers to the ear of the user only when an alarm is notified. (b) Prior art As a conventional clock of this kind, the Utility Model 1191
There were those shown in Japanese Utility Model Publication No. 61-96390. All of these watches are configured to be hung in advance near the user's ear and to rise simultaneously with an alarm notification. According to this watch, it rises to a place that is difficult for the user to reach at the same time as the alarm is activated.
The user cannot easily turn off the alarm and ends up getting up and waking up. (c) Problems to be Solved by the Invention In the above-mentioned conventional technology, as soon as the alarm notification starts, the watch moves away from the user, so the alarm sound gradually moves away and becomes audible. Therefore, if the user is not woken up when the alarm notification starts, there is a high possibility that the user will fall asleep even after the alarm notification starts. Also, at first glance, hanging a watch may seem less intrusive than placing it next to your bed, but in reality, if you have a watch hanging from your ear, the threads may get tangled in your body when you turn over. This caused problems such as the watch hitting the user's face, and furthermore, the watch swayed and the position of the watch could not be fixed, which caused problems such as getting in the way. (d) Means for Solving the Problems The purpose of the present invention is to provide an alarm clock with a lifting device that does not get in the way during use and has a higher wake-up effect. In order to solve the above-mentioned problems and achieve the purpose, the present invention has developed a drive section for driving a motor in an alarm clock with a lifting device, and a first drive circuit that rotates the motor to lower the clock. a second drive circuit that rotates the motor so as to raise the motor; a generation detection circuit that detects that a coincidence signal is output from the alarm circuit; and a first drive circuit that counts a certain period of time after the output detection signal is generated.
a timer circuit, an AND gate that supplies a coincidence signal from the alarm circuit to the sound generation circuit only when a count end signal is generated from the first timer circuit, and a disappearance detection circuit that detects disappearance of the coincidence signal from the alarm circuit. a second timer circuit that counts for a certain period of time after the output detection signal is generated; and a first drive circuit that operates from the time the coincidence signal is output until the first timer circuit finishes counting; The present invention is characterized in that it includes a drive control circuit that operates the second drive circuit from the time the coincidence signal disappears until the second timer circuit finishes counting. In other words, the clock of the present invention is normally hung near the ceiling, lowers to the user's ear as soon as an alarm is sounded, and rises to its original position and stops when the alarm is stopped. . (e) Examples Examples of the present invention will be described below based on the drawings. FIG. 2 is a perspective view showing the external appearance of an alarm clock with a lifting device according to an embodiment of the present invention, and FIG. 3 is a central vertical sectional view thereof. As shown in FIG. 2, the clock in this embodiment has a display section 4 provided on the front surface of the watch case 2 for displaying the time, and a ring stop switch 6 provided on the top surface of the watch case 2. It has a thread 8 pulled out from a hole 2a formed in the center of the upper surface of the watch case 2, and a hook member 10 attached to the end thereof. Further, as shown in FIG. 3, inside the watch in this embodiment, there is a motor 12 as a drive source, a reduction gear train mechanism 14 consisting of a group of gears that decelerates and transmits the rotation of the motor 12, and a thread 8. A pulley 16 is provided at the end of which is attached and rotationally driven by the reduction gear train mechanism 14. As shown in the figure, in the initial state, the thread 8 is wound around the pulley 16, and the hanging member 1
If you hang 0 on the ceiling, the clock will hang near the ceiling. In this state, when the set alarm time comes, the motor 12 is rotated by a current supplied from a drive section, which will be described later, and rotates the pulley 16 via the reduction gear train mechanism 14. At this time, the pulley 16 rotates in the direction of unraveling the thread 8, so that the watch gradually descends. Thereafter, when the alarm notification is stopped by operating the stop switch 6, etc., the motor is rotated in the opposite direction to the direction in which the clock is lowered, and the pulley 16 is thereby rotated in the direction to wind up the thread 8.
The clock rises. Next, the circuit configuration of the above-mentioned motor drive section and the like will be explained using FIG. 1. In the figure, 20 is a reference signal generator, and 22 is a frequency dividing circuit that divides the frequency of the reference signal output from the reference signal generator and outputs a clock signal. 24 is a time display section that inputs a clock signal to count and display the time; a clock counter 26 that inputs the clock signal and counts the time; and a decoder/driver 28 that converts the count contents into a display drive signal. , and a display section 30 that receives a display drive signal and displays the time. Reference numeral 32 designates an alarm circuit, including an alarm memory 34 that stores the set alarm time, and a matching circuit 36 that compares the stored content with the count content of the time counter 26 and outputs a signal when they match.
, a one-shot multivibrator (hereinafter referred to as OSM) 38 which outputs a pulse when its output signal is input, a flip-flop (hereinafter referred to as FF) 40 which inputs the output pulse to the set input S, and this FF 40. The signal from the output of the frequency divider circuit 22 is input to the reset input R.
A timer 42 inputs signal ₁ from the middle stage of FF 40 to the clock input and applies an output signal from the output C to the reset input R of FF 40;
It is composed of an AND gate 44 which inputs a signal from the output Q of the oscillator and a signal from a ring stop switch 46. 47 is a sound generation circuit that generates an alarm sound via an AND gate 49. Next, the configuration of the drive section that drives the motor will be explained. 48 is an occurrence detection circuit, and alarm circuit 32
OSM 5 generates a pulse in the output signal A when a match signal _b1 is generated at the output of the AND gate 44 in the OSM5.
It consists of 0. 52 is a disappearance detection circuit, and when the coincidence signal _b1 disappears, an inverter 54 inverts it and outputs it.
and an OSM 56 which outputs a pulse as the output signal B when its output becomes H level. 58 is a first timer circuit, which inputs the output signal A of the occurrence detection circuit 48 to the set input S, and inputs the output signal _a2 of the FF 68, which will be described later, to the reset input R, and the signal from the output thereof.
An _AND gate 62 which inverts and inputs both a1 and signal _a2 , an AND gate 64 which inputs its output signal _a3 and clock signal ₁ , a timer 66 which inputs its output signal to the clock input, and its output. C
The FF68 inputs the signal _a4 from the FF68 to the clock input and outputs the signal _a2 from the output Q. 70 is a second timer circuit, which inputs the output signal B of the erasure detection circuit 52 to the set input S and inputs the output signal _b3 of the OSM 78 (described later) to the reset input R, and a signal from the FF 72 and its output Q.
AND gate 74 inputting b ₂ and clock signal ₁
and a timer 76 which inputs its output signal to the clock input and inputs the signal _b3 to the reset input R.
and an OSM 78 which generates a pulse as a signal _b3 when the signal from its output C is input. Reference numeral 80 denotes a vertical movement instruction circuit comprising an AND gate 82 which inputs the signal _a2 and the signal ₂ from the intermediate stage of the frequency dividing circuit 22. 84 is a drive control circuit consisting of a JK type FF 86 having set/reset inputs. The coincidence signal b ₁ from the alarm circuit 32 and the signal a ₂ from the first timer circuit 58 are applied to the set input S and reset input R of this FF 86, respectively, and the clock input C is applied to the vertical movement instruction circuit 80. A signal from _A5 is applied. Furthermore, an H level signal is always applied to the J and K inputs. 88 is a first drive circuit, which is a transistor whose base inputs the signal from the output Q of the FF 86 via a resistor 92, and whose emitter and collector are connected to the power supply and the first input terminal of the motor 124, respectively. 90, a transistor 94 whose base receives the signal from the output Q of the FF86 via a resistor 96, whose emitter is connected to the power supply and whose collector is grounded via a resistor 98, and a resistor connected to the collector of the transistor 94. A base is connected through 102 and its collector is connected to a motor 124.
The transistor 100 is connected to the second input terminal of the transistor 100 and has its emitter grounded via a resistor 104. 106 is a second drive circuit, which inputs the signal from the output of the FF 86 to its base via a resistor 110, and includes a transistor 108 whose emitter and collector are connected to the power supply and the second input terminal of the motor 124, respectively. Then, the signal from the output of FF86 is input to the base via resistor 114, and its emitter is connected to the power supply and the collector is connected to resistor 1.
Transistor 112 connected to ground via 16
And a resistor 1 is connected to the collector of this transistor 112.
The transistor 118 has a base connected through a resistor 120, a collector connected to a first input terminal of a motor 124, and an emitter connected to ground through a resistor 122. Next, detailed elevating and lowering operations of the timepiece in this embodiment will be explained, focusing on the operation of the drive section having the above configuration. First, when the alarm time stored in the alarm memory 34 in the alarm circuit 32 arrives, the coincidence circuit 36 detects this and sets its output signal to H level. The OSM 38 outputs a pulse in response to this H level signal, and the FF 40 which inputs this pulse to the set input S is set. When the FF 40 is set and the signals from its output Q go to H and L levels, the timer 42 is reset and starts counting, and the AND gate 44 is opened. If the ring stop switch 46 is in the on state at this time, the coincidence signal _b1 output from the AND gate 44 becomes H level. Further, when the coincidence signal _b1 becomes H level, a pulse is generated in the output signal A of the generation detection circuit 48 in response to the rise of the coincidence signal b1. The FF 60 in the first timer circuit 58 is set by the pulse generated in the signal A, and makes the signal _a1 from its output L level. Therefore, the normally closed AND gate 62 becomes open and its output signal _a3 becomes H level. When this signal _a3 becomes H level, the AND gate 64 becomes open and the clock signal is sent to its output.
₁ occurs. This signal is applied to the clock input of timer 66 and timer 66 begins counting. On the other hand, the H level coincidence signal _b1 is generated by the drive control circuit 8.
It is also applied to FF86 in 4. The FF 86 is configured to have an output state as shown in the table depending on the state of its input signal.

[Table] ↓…Synchronized with falling edge
−
That is, the signals b ₁ and a ₂ applied to the set input S and reset input R of the FF 86 in the initial state
is at the L level, so the FF 86 keeps both the signals from its output AQ at the H level regardless of other input signals (operation order 1 in the table). When the signal from the output Q of the FF 86 is at H level, the transistors 90, 94, 108, 112 in the first drive circuit 88 and the second drive circuit 06 whose bases are supplied with this signal are non-conductive. , no current is supplied to the motor 124 and the clock is stopped. Now, the coincidence signal b ₁ becomes H level, and this signal b ₁
When input to the set input S, the FF 86 switches only the signal from its output Q to the L level (operation order 2 in the table). When the signal from the output Q of this FF 86 becomes L level, the transistor 9 in the first drive circuit 88
0 and 94 are in the pain conducting state. This transistor 9
4 becomes conductive, current also flows to the base of the transistor 100, and this transistor 100
also becomes conductive. Therefore, the motor 124 is connected to the transistor 90,
The motor 124 is connected to a current through the motor 100, and the current flows, for example, from the first input end to the second input end, and the motor 124 rotates so as to rotate the aforementioned pulley 16 in the direction of unraveling the thread. Therefore, the clock begins to descend. When the above state continues and the counting timer 66 in the first timer circuit 58 counts for a certain period of time and generates a pulse in the signal _a4 from its output C, the FF 68 outputs the signal in synchronization with the fall of the pulse. Set signal _a2 from Q to H level. this signal a ₂
When becomes H level, FF60 is turned off and sound generation circuit 47
An alarm sound will be sounded. In addition, since the signal _a2 input to the reset input R of the FF86 becomes H level, all the signals input to the inputs J, K, S, and R become H level, and this time, the signals input to the clock input C become H level. signal a ₅
The state of output Q is switched in synchronization with the falling edge of Q (operation order 3 and 4 in the table). Since the signal _a2 is at the H level, the AND gate 82 is in an open state, and the clock signal ₂ is generated as its output signal _a5 . Therefore, F.F.
The output state of 86 is switched depending on the period (for example, several seconds) of this clock signal ₂ . The output Q of this FF86 is L level, and the output is H
When the level is high, the transistors 90 and 100 in the first drive circuit 88 become conductive, similar to the operation described above, the motor 124 rotates and the clock falls, but the output Q of the FF 86 is at the H level and the output is at the L level. When switching to the level, the second drive circuit 106
The transistors 108, 112, and 118 in the motor become conductive, and current is supplied to the motor 124 so that the current flows from the second input terminal to the first input terminal. This causes the motor 124 to rotate in reverse, causing the clock to rise. Therefore, the clock moves down for a certain period of time,
When it reaches the user's bedside, it will move up and down at intervals of several seconds. The reason for this setting is to make it more difficult to grasp the clock that has descended to the ear, so that the user can wake up earlier. The above state continues, and the timer 42 in the alarm circuit 32 counts up and the FF 40 is reset, or the ring stop switch 46 is turned off and the AND gate 44 is closed, and the coincidence signal b ₁ goes to L level. When this occurs, the sound generation circuit 47 stops generating the alarm sound. Furthermore, when the match signal b ₁ becomes L level, this signal b ₁ is inverted by the inverter 54 in the erasure detection circuit 52, and in response to the rising edge of the inverted signal, the OSM 56 generates a pulse in its output signal B. let The pulse generated in this signal B is applied to the set input S of the FF 72 in the second timer circuit 70 to set it. Therefore, the output signal _b2 of the FF 72 becomes H level, and the AND gate 74 inputting this signal becomes open. A clock signal ₁ is generated at the output of the AND gate 74 in the open state, and a timer 76 inputting this signal to the clock input starts counting. On the other hand, the FF 86 in the drive control circuit 84 changes only its output to the L level, regardless of the states of the inputs J, K, and C, since the match signal _b1 input to its set input S becomes L level. level (table action order 5). When the output of this FF 86 becomes L level, the second drive circuit 106 operates in the same manner as described above.
As a result, the motor 124 is driven and the clock moves upward. Thereafter, the timer 76 in the second timer circuit 70 counts up and sets its output C to the H level, and in response, the OSM 78 generates a pulse in its output signal _b3 . This pulse is applied to each reset input R of FF72, timer 76, and timer 66, FF68 to reset them. As a result, FF6
The output signal _a2 of 8 becomes L level. As mentioned above, when the signals a ₂ and b ₁ both go to L level, the FF 86 to which they are input returns to the initial state again, and its outputs Q both go to H level, so that the first and second drive circuit 88, 10
All transistors in 6 become non-conducting,
The motor 124 stops (operation order 6 in the table). As described above, the watch in this embodiment starts descending as soon as the alarm is reported, moves up and down when it reaches the user's ear, and rises and stops at the original position when the alarm stops. This is what I did. (f) Effects of the invention According to the invention, since the alarm is stopped at a high place except when an alarm is reported, it does not get in the way. In addition, since the alarm sounds are lowered to the user's ears along with the alarm notification, the user can hear the alarm sound gradually louder, which has a high wake-up effect. Furthermore, since it automatically rises and stops when the alarm notification is stopped, the user does not have to take up the trouble of winding up the thread after the alarm notification.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the circuit configuration of an alarm clock with a lifting device according to an embodiment of the present invention, Fig. 2 is an external view of the alarm clock with a lifting device, and Fig. 3 is a central longitudinal section of the clock shown in Fig. 2. It is a front view. 8... Thread, 10... Hanging member, 12, 124...
... Motor, 14 ... Reduction gear train mechanism, 16 ... Pulley, 28 ... Time display section, 32 ... Alarm circuit, 46 ... Sound stop switch, 48 ... Occurrence detection circuit, 52 ... Disappearance detection circuit, 58...first timer circuit, 70...second timer circuit, 8
0... Vertical movement instruction circuit, 84... Drive control circuit,
88...first drive circuit, 106...second drive circuit.

Claims (1)

[Scope of Claim for Utility Model Registration] A reference signal generator, a frequency dividing circuit that divides the frequency of the reference signal, a time display section that displays the time in response to the output signal from the frequency dividing circuit, and an alarm silence switch. an alarm circuit that outputs a coincidence signal for a certain period of time only when the alarm silence switch is in an on state; a sound generation circuit that emits a sound when a coincidence signal is output from the alarm circuit; a motor; and a rotation shaft of the motor. a reduction gear train mechanism connected to the motor to reduce shaft rotation of the motor; a pulley connected to the reduction gear train mechanism; one end attached to the pulley and the other end attached to a latching member for supporting the watch body. In an alarm clock with a lifting device, the alarm clock includes a thread attached to the pulley and a drive unit that drives the motor in response to generation of a coincidence signal from the alarm circuit, wherein the drive unit moves the thread wound around the pulley. a first drive circuit that rotates the motor in the direction of unwinding the thread; a second drive circuit that rotates the motor in the direction of winding the thread around the pulley; and a generator that detects that a coincidence signal is output from the alarm circuit. a detection circuit; a first timer circuit that counts for a certain period of time from when the detection signal from the occurrence detection circuit is generated; and a coincidence signal from the alarm circuit only when a count end signal is generated from the first timer circuit. an AND gate that can be supplied to the alarm circuit; a disappearance detection circuit that detects disappearance of the coincidence signal output from the alarm circuit; and a count for a certain period of time from when the detection signal from the disappearance detection circuit is generated. a second timer circuit that operates the first drive circuit until the first timer circuit counts for a certain period of time after the coincidence signal is output from the alarm circuit; An alarm clock with a lifting device, comprising: a drive control circuit that operates the second drive circuit until the second timer circuit counts for a certain period of time after the signal disappears.