JPH0442919Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the structure of a transistor incorporating a lateral reach-through type avalanche diode.

[Conventional technology]

It is known to construct a Darlington transistor as shown in FIGS. 4-6. In the figure, 1 is a semiconductor substrate made of silicon, 2 is an n ⁺ type region which becomes a collector low resistance region, 3 is an n ^- type region which is a collector high resistance region, 4 is a p type region which is a base region, and 5 is a drive region. An n ⁺ -type region becomes the emitter region of the stage transistor Tr ₁ ; 6 is an n ⁺ -type region which becomes the emitter region of the output stage transistor Tr ₂ ; 7 is an n ⁺ -type region which becomes the peripheral region; and 8 is an SiO ₂ film.
P type region 4 and n ⁺ type regions 5, 6, and 7 are formed by impurity diffusion. 9, 10, and 11 are electrodes made of Al, 9 is the base electrode of the Darlington transistor, 10 is the electrode connecting the emitter of the drive stage transistor Tr ₁ and the base of the output stage transistor Tr ₂ , and 11 is the emitter electrode of the Darlington transistor. It is. 12 is a collector electrode of a Darlington transistor having a three-layer structure of Ti-Ni-Ag. Note that in FIG. 4, the SiO ₂ film 8 is depicted as if it were transparent, and the electrodes 9, 1
0 and 11 are marked with diagonal lines to distinguish them from the others.

FIG. 6 shows an equivalent circuit of this Darlington transistor. Resistors R ₁ and R ₂ are commonly connected to improve temperature stability. _R1 is
This is obtained by the resistance of the p-type region 4 between the base electrode 9 and the electrode 10 that short-circuits the n ⁺ -type region 5 and the p-type region 4. R ₂ is a p-type electrode between the emitter electrode 11 and the electrode 10 extending in a part 4a of the p-type region 4 exposed like an island in the n ⁺ type region 6 which becomes the emitter region of the output stage transistor. obtained by the resistance of region 4. The protective diode D prevents a voltage higher than a predetermined value from being applied between the collector C and the base B of the Darlington transistor, and protects the p-type region 4-n ^- type region 3-n ⁺ -type region 7a. Therefore, it is formed in the horizontal direction. however,
The n ⁺ type region 7a and the collector electrode 12 are vertically connected by the n ⁻ type region 3 and the n ⁺ type region 2.

The n ⁺ type region 7a for configuring the protection diode D is a part of the peripheral n ⁺ type region 7 and is provided along the first side 13 of the semiconductor substrate 1 having a quadrilateral (square) planar shape. It is being That is, the first
The width l ₁ of the n ^- type region 3 between the n ⁺ type region 7a and the p type region 4 along the side 13 ^of The width is set narrower than the width of the n ^- type region 4 between the region 7 and the p-type region 4.

When a reverse voltage is applied between the collector and base of the Darlington transistor including the protection diode D as described above, the space charge layer is removed from the p-type region 4 side.
Extends to n ^- type region 3. As the reverse voltage is increased, at a certain voltage value, the space charge layer reaches the n ⁺ type region 7a at a portion having a width _l1 . When the reverse voltage is further increased, the electric field strength in the space charge layer between the p-type region 4 and the n ⁺ -type region 7a increases rapidly at a portion of width l ₁ and exceeds a critical value, resulting in a so-called reach-three type. causes an avalanche breakdown. The breakdown voltage V _B at this time depends on the depth of the n ⁺ type region 7a and the p type region 4, the specific resistance (impurity concentration) of the n ^- type region 3, and the width _l1 of the n ^- type region 3. Primarily determined.

[Problem that the invention attempts to solve]

By the way, there is a certain error Δl in the width l ₁ due to the accuracy of photomask alignment when forming the n ⁺ type region 7a based on the pattern of the p type region 4 already formed by impurity diffusion. This is unavoidable, and l ₁ =l±△l (l is the design value). Now, if the maximum deviation (error) is ±△ _lM , _l1 will vary with an error within the range of 2△ _lM from -△ _lM to +△ _lM . Therefore, an error in the breakdown voltage V _B also occurs corresponding to 2Δl _M. For example, if the depth of n ⁺ type region 7 is
15 μm, impurity concentration in n ^- type region 3 is approximately 10 ¹⁴ particles/cm ³ ,
When the surface impurity concentration of the p-type region 4 is approximately 10 ¹⁸ /cm ³ , the depth of the p-type region is 30 μm, and l is 55 μm, and the photomask alignment accuracy is ±5 μm, the breakdown voltage V _B is 400 ± It became 105 (V). Therefore, when the breakdown voltage V _B of the protection diode D is strictly required (when the tolerance of V _B is small), there are many defects at the characteristic check stage, and the manufacturing yield decreases.

If the protection diode D is formed in the vertical direction of the semiconductor substrate, the error in the breakdown voltage V _B can be reduced, but the manufacturing and structure become complicated. When the protection diode D is formed horizontally as in this example,
Since it is sufficient to form n ⁺ type region 7a by impurity diffusion at the same time as n ⁺ type regions 5 and 6, manufacturing and structure are simplified.

Therefore, the purpose of the present invention is to reduce the variation in the breakdown voltage V _B of a lateral reach-through type avalanche diode built into a transistor chip as a protection diode compared to the conventional one.

[Means for solving problems]

To achieve the above object, the present invention will be described with reference to the reference numerals in the drawings showing the embodiments. At least first, second, third, fourth, and fifth semiconductor regions 3, 4, 5, 7a, and 6 are provided in a semiconductor substrate 1 having a principal surface of and the fifth semiconductor regions 3, 5, 7a, and 6 are formed to have one conductivity type, and the second semiconductor region 4 is formed to have the other conductivity type opposite to the one conductivity type, and the first semiconductor region 3 has a portion exposed to the main surface and a portion extending parallel to the main surface, the second semiconductor region 4 is provided within the first semiconductor region 3, and the third and fifth semiconductor regions semiconductor regions 5 and 6 are provided in the second semiconductor region 4, and the fourth semiconductor region 7a is provided in the strip-shaped first semiconductor region between the second semiconductor region 4 and the main surface. 3 is provided in the first semiconductor region 3 and has a higher impurity concentration than the first semiconductor region 3,
A first transistor in which the first semiconductor region 3 is a collector region, the second semiconductor region 4 is a base region, and the third semiconductor region 5 is an emitter region, and the first semiconductor region 3 is a collector region. ,
The second semiconductor region 4 is a base region, and the fifth semiconductor region 4 is a base region.
In a composite semiconductor device having a Darlington transistor configuration, the second transistor has a semiconductor region 6 as an emitter region. The first, second, third, fourth, and fifth
The semiconductor regions 3, 4, 5, 7a, and 6 are arranged substantially symmetrically, and the third semiconductor region 5 is connected to the first side 13 and the fifth semiconductor region 6 on the virtual straight line. The fourth semiconductor region 7a for obtaining a lateral reach-through type avalanche diode is located between the third semiconductor region 5 and the fifth semiconductor region 6 on the main surface. and the second and fourth sides 14, 16, respectively,
The present invention relates to a composite semiconductor device characterized in that a narrow portion of the first semiconductor region 3 is provided between the fourth semiconductor region 7a and the second semiconductor region 4.

[Effect]

In the present invention, since a lateral reach-through type avalanche diode is formed along each of the two opposing sides 14 and 16, the lateral reach-through type avalanche diode is formed along each of the two opposing sides 14 _and 16. The width of one semiconductor region 3 (the base width of the diode) is the distance in the direction along the other two opposing sides, which is one of the reference directions for alignment in photomask alignment. Therefore, if the widths of the first semiconductor region 3 in the diode formation region along each of the two opposing sides are l ₂ and l ₃ , then if one of l ₂ and l ₃ is increased, the other becomes smaller. . That is, when l ₂ = l + Δl, l ₃ = l - Δl, and conversely, when l ₂ = l - Δl, l ₃ = l + Δl. On the other hand, breakdown occurs at the narrower of widths l ₂ and l ₃ . Therefore,
The width in which a positive error occurs is irrelevant to the breakdown. As a result, the width change range related to breakdown is from l to l-Δl, which is half of the conventional width. This means that the error (range of variation) in breakdown voltage becomes smaller.

〔Example〕

Next, a Darlington transistor according to an embodiment of the present invention will be explained based on FIGS. 1 to 3 and FIG. 6. However, parts common to FIGS. 4 and 5 are designated by the same reference numerals and their explanations will be omitted.
The Darlington transistors shown in FIGS. 1, 2, and 3 are constructed to obtain the equivalent circuit shown in FIG. 6 in the same manner as in the prior art. However, unlike the conventional example shown in FIG. 4, the formation region of the protection diode D is provided along the sides 14 and 16 of the silicon chip 1. That is, the p-type region 4 functioning as the base region of the drive stage transistor Tr ₁ and the side 14,
16, n ^- type region 3 and n ⁺ type region 7 with widths l ₂ and l ₃ .
A and a are provided, respectively, and are configured to function as a protection diode D. Sides 14, 16
In order to generate a protection diode function in a region _of width _{l 2} and l ₃ along
<l It's becoming ₁ . In order to obtain n ^- type regions 3 with narrow widths l ₂ , l ₃ on both sides of the drive stage transistor Tr ₁ , n ⁺
The width of the type region 7a is wider than the other n ⁺ type regions 7. Since the n ⁺ type region 7 is also provided along the side 13, a diode is formed between the p type region 4 and the n ⁺ type region 7 in terms of shape;
Since the width l ₁ is larger than l ₂ and l ₃ , breakdown occurs at the width l ₂ or l ₃ portion, but not at the width l ₁ portion.

In the Darlington transistor shown in Figure 1,
If l ₂ and l ₃ meet their target values, l ₂ = l ₃ = l, breakdown will occur in both the l ₂ and l ₃ regions in principle. But usually due to error l ₂ and l ₃
There is a difference between In this case, avalanche breakdown occurs in the narrower region between l ₂ and l ₃ . Therefore, the breakdown voltage V _B
is determined depending on the smaller value of l ₂ and l ₃ .

By the way, l ₂ and l ₃ are side 1, which is one reference direction for alignment in photomask alignment.
3 and 15, so if one becomes larger, the other becomes smaller. In other words, an error of +△l occurs in one l ₂ , and l ₂ = l + △
If it becomes l, an error of -△l will occur in the other l ₃ , and l ₃
=l−△l. And the breakdown voltage
V _B is determined by the narrower of l ₂ and l ₃ . The width error range related to breakdown is l to l−△
1, which is 1/2 compared to Fig. 4. Difference (deviation) of breakdown voltage V _B from target value
corresponds to the width change range l-l-Δl, so theoretically it will be about 1/2 of that in the case of FIG.

A Darlington transistor was fabricated under substantially the same conditions as the conventional example shown in Figure 4, except for the dimensions l ₁ , l ₂ , and l ₃ , and the maximum deviation of the breakdown voltage V _B was determined, and the target value was 350 V. In contrast, it was ±65V, which was significantly smaller than in Figure 4. When the center value of V _B needs to be the same as before, 400V,
Slightly increase the target width l. This results in
A characteristic of V _B =400±65V can be obtained.

Although the length along sides 14 and 16 of the l ₂ and l ₃ regions is shorter than the length along side 13 of the l ₁ region, a large current flows toward the base of the drive stage transistor Tr _1. Since the current does not normally flow, the problem of insufficient current capacity does not occur.

[Modified example]

The present invention is not limited to the embodiments described above, but can take other variations.
For example, in FIG. 1, l ₁ =l ₂ =l ₃ may be set. Even with this setting, avalanche breakdown still occurs at the narrowest width portion, and the variation width will never become larger than Δl. In addition, the output stage transistor Tr ₂ in Fig. 6
It is also applicable to the case where a protection diode is provided between the collector and base of. In this case,
Width relative to p ⁺ type area 4 on both left and right sides of n ⁺ type area 6
N ⁺ type regions 7a are provided along sides 14 and 16 with intervals corresponding to l ₂ and l ₃ . In this case, additional side 1
n ⁺ type region 7a with a width corresponding to l ₁ along 5
may be provided.

[Effect of idea]

According to the present invention, the variation range of the breakdown voltage V _B of the protection diode with respect to the target value is reduced, and it becomes possible to manufacture transistors having a breakdown voltage V _B within an allowable range with a high manufacturing yield. . Furthermore, since the structure can be realized by simple changes in the element pattern arrangement, there is no cause for cost increase.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a Darlington transistor according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line -- in FIG. 1, FIG. 3 is a cross-sectional view taken along the line -- in FIG. A plan view showing a Darlington transistor, FIG. 5 is a sectional view taken along the line - in FIG. 4,
FIG. 6 is an equivalent circuit diagram of the Darlington transistor shown in FIGS. 1 and 4. FIG. 3...n ^- type region, 4...p-type region, 5...n ⁺
type area, 6...n ⁺ type area, 7a...n ⁺ type area,
9... Base electrode, 11... Emitter electrode, 12
...Collector electrode.

Claims (1)

[Claims for utility model registration] First, second, third and fourth sides 13, 14, 1
At least first, second, third, fourth and fifth semiconductor regions 3, 4, 5, 7 in semiconductor substrate 1 having a square or rectangular main surface consisting of 5, 16
a, 6 are provided, the first, third, fourth and fifth semiconductor regions 3, 5, 7a, 6 are of one conductivity type, and the second semiconductor region 4 is of the opposite conductivity type to the one conductivity type. The first semiconductor region 3 has a portion exposed to the main surface and a portion extending parallel to the main surface, and the second semiconductor region 4 has the other conductivity type. 1 semiconductor region 3, the third and fifth semiconductor regions 5 and 6 are provided in the second semiconductor region 4, and the fourth semiconductor region 7a is provided in the second semiconductor region 7a on the main surface. The strip-shaped first semiconductor region 4
is provided in the first semiconductor region 3 such that a semiconductor region 3 is interposed therebetween and has a higher impurity concentration than the first semiconductor region 3, and the first semiconductor region 3 is a collector region and the first semiconductor region 3 is a collector region. A first transistor in which the semiconductor region 4 of No. 2 is a base region, the third semiconductor region 5 is an emitter region, the first semiconductor region 3 is a collector region, the second semiconductor region 4 is a base region, and the third semiconductor region 5 is an emitter region. In a composite semiconductor device having a Darlington transistor configuration including a second transistor having a fifth semiconductor region 6 as an emitter region, the center of the first side 13 of the main surface and the first side
The first, second, third, fourth and fifth semiconductor regions 3, 4, 5, 7 are centered on a virtual straight line connecting the center of the third side 15 opposite to the side 13 of
a, 6 are arranged substantially symmetrically, and the third semiconductor region 5 is connected to the first side 13 and the fifth semiconductor region 6 on the virtual straight line.
The fourth semiconductor region 7a for obtaining a lateral reach-through type avalanche diode is located between the third semiconductor region 5 and the fifth semiconductor region 6 on the main surface. and the second and fourth sides 14 and 16, respectively, and the first semiconductor region 7a is provided between the fourth semiconductor region 7a and the second semiconductor region 4. A composite semiconductor device characterized in that a narrow portion of a semiconductor region 3 is provided.