JPH0447756U - - Google Patents
Info
- Publication number
- JPH0447756U JPH0447756U JP8991390U JP8991390U JPH0447756U JP H0447756 U JPH0447756 U JP H0447756U JP 8991390 U JP8991390 U JP 8991390U JP 8991390 U JP8991390 U JP 8991390U JP H0447756 U JPH0447756 U JP H0447756U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- main memory
- bus
- master
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006870 function Effects 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims 1
- 230000004044 response Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
Landscapes
- Multi Processors (AREA)
Description
第１図は本考案の一実施例の構成ブロツク図、
第２図〜第５図はそれぞれＣＰＵ、デイバイスの
アクセス状態に於ける動作の一例を示すタイムチ
ヤート、第６図は従来装置の構成ブロツク図であ
る。
１……スヌープ機能を備えたＣＰＵ、２……マ
スタとなり得るデイバイス、３……メモリユニツ
ト、１１……キヤツシユ、３１……主記憶部、３
２……ラインアクセス記憶部、３３……スヌープ
起動部、３４……主記憶禁止信号発生部、ＢＳ…
…バス。
FIG. 1 is a block diagram of an embodiment of the present invention.
FIGS. 2 to 5 are time charts showing examples of operations in the access state of the CPU and devices, respectively, and FIG. 6 is a block diagram of the configuration of the conventional device. 1...CPU with snoop function, 2...Device that can be a master, 3...Memory unit, 11...Cache, 31...Main storage section, 3
2...Line access storage section, 33...Snoop starting section, 34...Main memory inhibition signal generation section, BS...
…bus.
Claims (1)
たＣＰＵと、このＣＰＵにバスを介して接続され
ＣＰＵに代わつてマスタとなり得るデイバイスと
、前記バスに接続されるメモリユニツトとで構成
されたマルチマスタシステムにおいて、 前記メモリユニツトは、 システムの主記憶となるメモリエリアを有する
主記憶部と、 前記デイバイスがマスタとなつてラインをアク
セスしたのを検出しそれを記憶するラインアクセ
ス記憶部と、 このラインアクセス記憶部がラインアクセスを
検出したのを受けて、リードアクセス時に前記Ｃ
ＰＵのスヌープ機能をイネーブルにするスヌープ
起動部と、 メモリユニツトがアクセスされるのを検出し、
前記バス上のクロツクとメモリ禁止信号とを受け
て前記主記憶部に対して主記憶禁止信号を出力す
る主記憶禁止信号発生部と を備えることを特徴とするメモリ装置。[Claims for Utility Model Registration] Consisting of a CPU that has a cache and a snoop function, a device that is connected to this CPU via a bus and can act as a master in place of the CPU, and a memory unit that is connected to the bus. In the multi-master system, the memory unit includes a main memory section having a memory area that serves as the main memory of the system, and a line access memory section that detects when the device serves as a master and accesses a line and stores it. In response to this line access storage unit detecting a line access, the above-mentioned C
A snoop activation part that enables the snoop function of the PU and detects when the memory unit is accessed.
A memory device comprising: a main memory inhibit signal generating section that receives a clock on the bus and a memory inhibit signal and outputs a main memory inhibit signal to the main memory section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8991390U JPH0447756U (en) | 1990-08-28 | 1990-08-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8991390U JPH0447756U (en) | 1990-08-28 | 1990-08-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0447756U true JPH0447756U (en) | 1992-04-23 |
Family
ID=31824236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8991390U Pending JPH0447756U (en) | 1990-08-28 | 1990-08-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0447756U (en) |
-
1990
- 1990-08-28 JP JP8991390U patent/JPH0447756U/ja active Pending
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