JPH0447759U - - Google Patents

Info

Publication number
JPH0447759U
JPH0447759U JP9059890U JP9059890U JPH0447759U JP H0447759 U JPH0447759 U JP H0447759U JP 9059890 U JP9059890 U JP 9059890U JP 9059890 U JP9059890 U JP 9059890U JP H0447759 U JPH0447759 U JP H0447759U
Authority
JP
Japan
Prior art keywords
storage means
data signal
host computer
circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9059890U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9059890U priority Critical patent/JPH0447759U/ja
Publication of JPH0447759U publication Critical patent/JPH0447759U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案に係るデータ信号転送装置の
好適な実施例の全体概略構成図である。 1はホストコンピユータ、2,4,6はデユア
ルポートRAM、3,5,7はサブコンピユータ
、9,11,13はオア回路、ABはアドレスバ
ス、DBはデータバス、L1,L2,L3,Lc
は信号ラインである。
FIG. 1 is an overall schematic diagram of a preferred embodiment of a data signal transfer device according to the present invention. 1 is a host computer, 2, 4, 6 are dual port RAMs, 3, 5, 7 are sub computers, 9, 11, 13 are OR circuits, AB is an address bus, DB is a data bus, L 1 , L 2 , L 3 , Lc
is a signal line.

Claims (1)

【実用新案登録請求の範囲】 ホストコンピユータからデータ信号が転送され
る複数のサブコンピユータに各々備えられた記憶
手段と該ホストコンピユータとの間にオア回路が
設けられ、 全てのサブコンピユータに必要な共通データ信
号の上記記憶手段への書き込みを許可する第1の
信号、または特定のサブコンピユータに必要な特
定データ信号の該記憶手段への書き込みを許可す
る第2の信号が、上記オア回路を介して上記ホス
トコンピユータから該記憶手段に与えられる、 ことを特徴とするデータ信号転送装置。
[Claims for Utility Model Registration] An OR circuit is provided between the storage means provided in each of a plurality of subcomputers to which data signals are transferred from the host computer and the host computer, and a common OR circuit required for all the subcomputers is provided. A first signal for permitting writing of a data signal into the storage means, or a second signal for permitting writing of a specific data signal necessary for a particular subcomputer into the storage means, is transmitted through the OR circuit. A data signal transfer device, characterized in that the data signal is transmitted from the host computer to the storage means.
JP9059890U 1990-08-29 1990-08-29 Pending JPH0447759U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9059890U JPH0447759U (en) 1990-08-29 1990-08-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9059890U JPH0447759U (en) 1990-08-29 1990-08-29

Publications (1)

Publication Number Publication Date
JPH0447759U true JPH0447759U (en) 1992-04-23

Family

ID=31825494

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9059890U Pending JPH0447759U (en) 1990-08-29 1990-08-29

Country Status (1)

Country Link
JP (1) JPH0447759U (en)

Similar Documents

Publication Publication Date Title
JPS6335152U (en)
HK36994A (en) Apparatus for read handshake in high-speed asynchronous bus interface
EP0217479A3 (en) Information processing unit
JPS59192765U (en) Noise removal structure of tablet input device
JPS6217879Y2 (en)
JPS6071964U (en) Dual port RAM
JPS6151548U (en)
JPH0120781B2 (en)
JPS6214536U (en)
JPS6211753B2 (en)
JPS61185142U (en)
JPS58108547U (en) data transfer device
JPS6281253U (en)
JPS58174748U (en) Synchronous signal lead connection circuit
JPS6368054U (en)
JPH03107736U (en)
JPH02116346U (en)
JPS61204267U (en)
JPH02149448U (en)
JPS6057127U (en) Electron beam lithography equipment
JPS60502073A (en) Circuit device that combines one-chip microprocessor
JPH0286250U (en)
JPH0521376B2 (en)
JPS59147236U (en) Interface control device
JPS60642U (en) input/output control device