JPH0449727A - Multiframe alignment circuit - Google Patents

Abstract

PURPOSE:To shorten the delay time of a single frame system data by writing reception data on a RAM according to a multiframe phase, and selecting RAM output according to a multiframe phase value or a counter value. CONSTITUTION:The read/write of reception input data on the RAM 1 is performed according to the multiframe(MF) phase, and the synchronous pattern of the MF is detected from readout data, and the frame phase and an MF phase are latched with a latch circuit 20. MF system data to which MF alignment is applied can be obtained by selecting the output of the RAM 1 according to a latched MF phase value, and the single frame(SF) data to which frame alignment is applied can be obtained by selecting the output of the RAM 1 according to the value of an MF counter 24. In such a way, MF synchronization and the MF alignment on the MF system data can be performed by one RAM 1, and frame synchronization and the frame alignment on the SF system data can be performed. Therefore, it is possible to suppress the delay time of the SF system data within one frame transmission time at maximum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-frame alignment circuit, and more particularly to a multi-frame alignment circuit designed to reduce the delay time of single-frame data.

[Conventional technology]

An example of a conventional multi-frame alignment circuit is shown in FIG. 6 and will be described.

FIG. 6 is a block diagram showing a multi-frame alignment circuit incorporating a conventional multi-frame synchronization circuit disclosed in, for example, Japanese Patent Publication No. 1-276839.

In the figure, 1 is a random access memory (hereinafter referred to as RAM) for temporarily storing received input data.
The RAM 1 has a capacity to store received data for at least one multiframe. 2 is a frame counter for writing received input data, and this 7-frame counter 2 is a frame counter that operates at an arbitrary phase.

3 output is a comparator that compares whether the output data of Ml matches the multi-frame synchronization pattern, 4 is a protection circuit that performs forward protection and backward protection, 5Fi reception input synchronization frame counter, 6 is reception input synchronization multi Frame counter, T is a gate that prohibits counting up during hunting, 8 is a memory for multi-frame alignment, 9 is a reception output external synchronization frame counter, 10 is a reception output external synchronization multi-frame counter, 11 is reception phase address and external phase address 12 is a 7-frame alignment memory, 13 is a single/multiframe data information instruction memo IJ14/Ii that stores information for identifying single frame data and multiframe data.
This is a selection circuit that selects between single-frame data and multi-frame data.

Next, the operation of the multi-frame alignment circuit shown in FIG. 6 will be explained with reference to FIG. 7.

FIG. 7 is a frame configuration diagram for explaining the operation of FIG. 6. Here, the /ri20 frame counter 5 is a 193-stage paste/g counter. Then, when 193 clocks are counted, a carried output that becomes a frame reference is generated. Furthermore, the multi-frame counter 6 is a 20-stage clock counter, and counts 20 clocks in synchronization with the carrier output supplied from the frame counter 5; generate. That is, when the two-lume counter 5 and the multi-frame counter 6 are combined, they can be regarded as a counter with 3860 (193 to 20) stages. Here, the configuration is such that the output of the multi-frame counter 6 is used to output the full detection pulse a when the (193x 1911=)3668th count is detected.

When the synchronization is lost, a detection pulse a indicating that 3668 counts have been detected is supplied to the gate 7, thereby completely preventing the 7 frame counter from increasing by 50 counts. Therefore, the frame counter 5 continues to stop counting at the 3668th count.Next, when the hunting operation is started, the data stream is taken into an arbitrary address in the RAM1. Then, data #'i that has been taken into RAM1 is transferred to RAM by a data shift circuit (not shown) as D19→D18→...Do as shown in FIG.
The input port of 1 is shifted by 1 bit to SB* and re-fetched. That is, in addresses containing the synchronization pattern F bit, the synchronization pattern F bit is rotated within the same address.

Next, comparator 3, which detects the received synchronization butter, constantly monitors the data output from RAM1, and detects this when the synchronization pattern contained in the F bits is in the desired arrangement. It detects and outputs a synchronization pattern detection pulse bl. Then, by supplying this synchronization pattern detection pulse b to the gate T, the detection pulse output tube for the 3668 count that continues to be output from the gate T is temporarily inhibited. At this time, the frame counter 5 and the multi-frame counter 6 restart counting from the 3668th count. Here, the frame counter 5 and the multi-frame counter 6 become K when starting from the O first bit of the 20th frame.

Here, the synchronization pattern detection pulse b, which is in the hunting state, and the detection pulse 1, which indicates 3668 counts, are at the same position. Therefore, the count-up inhibit pulse is not output from the gate T.

Further, after the synchronization is pulled in, the output of the protection circuit 4 prevents the output of the count-up inhibit pulse from the gate 1.

That is, after correctly detecting the synchronization pattern tube, the 7-frame counter 5 and the multi-frame counter 6 are always
It keeps counting up.

The carrier output of the multi-frame counter 6 is synchronized with the first bit of the multi-frame and continues to operate in this state.

Therefore, multi-frame synchronization has been established for the received input data stream.

Next, ffK, multi-frame alignment operation, and 7-frame alignment operation will be explained.

Here, in the received input data stream, it is assumed that the received output and the 9-channel input are bit synchronized, and that the received output and the received input differ only in the bit phase within the multiframe. i.e. Multifla Air 2 Iment and 7
Frame alignment is to compensate for bit phase differences within a multiframe and within a frame between input and output of received data.

Therefore, this is done using the multi-frame alignment memory 8 and the 7-frame alignment memory 12.

First, the multi-7 frame alignment uses the first half of the clock period of the data stream to input received input data into a multi-frame alignment memory indicated by a frame counter 5 and a multi-frame counter 6 that indicate the phase of the received input data stream. Write to address 8. Then, using the second half of the clock cycle, the multi-frame received output data stream is read from the address in the multi-frame alignment memory 8 indicated by the frame counter 9 and multi-frame counter 10 that indicate the phase of the received output data stream. .

(9) For frame alignment, the received input data is written to the address of the frame alignment memory 12 indicated by the frame counter 5 indicating the phase of the received input data stream using the first half of the clock cycle of the data stream. Then, using the second half of the clock cycle, the single frame received output data stream is read from the address in the frame alignment memory 12 indicated by the frame counter 9 indicating the phase of the received output data stream.

The multi-frame data and single-frame data thus obtained are selected and received by the selection circuit 14 in accordance with the output of the single/multi-frame data information instruction memory 13, which is a multi-frame/single-frame specification memory. This becomes the output. In addition, in FIG. 6, C indicates a synchronization state signal, and d indicates a multi-frame pulse.

[Problem to be solved by the invention]

Conventional multi-frame alignment circuits such as the one described above have problems with single-frame data. In order to reduce the time required by 9 hours, a memory for frame alignment was required in addition to a memory for multi-frame alignment, which resulted in an increase in circuit scale. Just in case you don't have a memory for frame alignment, there is the problem that single frame data will be delayed by up to one multiframe transmission time, just like multiframe data.

This invention was made with the aim of solving such problems, and it is possible to suppress the delay time of single frame data to within the maximum transmission time of one frame, and also to reduce the circuit scale since there is no separate memory for frame alignment. The purpose of the present invention is to obtain a multi-frame alignment circuit that can be small in size.

[Means for Solving the Problems] A multi-frame alignment circuit according to the present invention receives data in which predetermined multi-frame synchronization patterns are distributed at regular intervals in a multi-frame consisting of a plurality of frames, and The received input phase information is detected from the periodic pattern mentioned above using a multi-point monitoring method, and based on the detected information, frame alignment is performed for single-frame data, and multi-frame alignment is performed for multi-frame data. a first 2-band access memory having a capacity t for storing received data for at least one multiframe;
A ratio W unit that detects a synchronization pattern in the output sent from this first random access memory, and a reception input that generates a multi-frame pulse whose reception input phase is synchronized by being driven by the output of this comparator. A phase-synchronized multi-frame counter, a latch circuit that stores information on the phase difference between input and output using the multi-frame pulse of the received input phase-synchronized multi-frame counter, and an i that operates according to the phase difference between the input and output stored in this latch circuit. A multi-frame counter for lute frame data, a multi-frame counter for single-frame data, an output phase-synchronized multi-frame counter, an output of the above-mentioned multi-frame counter for multi-7 REM-based data, and an output of the above-mentioned output phase-synchronized multi-frame counter. a switching circuit that completely switches and outputs the output to the first random access memory; a second random access memory that stores information for identifying single-frame data and multi-frame data; a first selection circuit that selects either a single frame data selection signal or a multiframe data selection signal according to the output of the memory; The device includes a second selection circuit that selects data.

[For production]

In accordance with this invention, received input data is written to and read from RAM according to the multi-frame to be read, a synchronization pattern of the multi-frame of the received input data is detected from this read data, and the next readout after this detection is performed. Since the data phase of the multi-frame to be read is the beginning of the received data, the frame phase and multi-frame phase are latched, and at the beginning of the multi-frame to be read (address 0), data is read from the address of the latched frame phase and the latched multi-frame is By selecting the RAM output according to the frame phase value, multiframe aligned multiframe data can be obtained, and when the multiframe phase counter to be read is reset, it is reset and incremented at the beginning of the frame of the received input data. By selecting the RAM output according to the multi-frame counter value to be processed, frame-aligned single frame data can be obtained, so multi-7 frame synchronization and multi-frame alignment can be performed for multi-7 frame data in one RAM. By performing frame synchronization and 7-frame alignment for single-frame data, the delay time for single-frame data can be suppressed to within the maximum 17-frame transmission time, and the circuit size can also be reduced. It can be done without making it bigger.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a multi-frame alignment circuit according to the present invention.

(In Figure Dfa1, those with the same symbols as in Figure 6 indicate corresponding parts, 15 is a protection circuit 11 that performs backward protection as in the previous issue Protection 1 and indicates a synchronization state and a hunting state, and 16 is a frame of received input data. 11 is a multi-frame counter that indicates the frame phase within the multi-frame of 9 input data; 18 is a gate for resetting the 7-frame counter 1s and the multi-frame counter IT; 19 is a comparator that detects the synchronization pattern in the output sent from RAM 1.The multi-frame counter 17 is driven by the output of the comparator 19, and receives the input phase-synchronized multi-frame pulse tube. Generates and receives input phase synchronized multi-frame counter.

20 is this received input phase synchronized multi-frame counter 1
A latch circuit 21 stores information on the phase difference between input and output using the multi-frame pulse from T, and 21 is a multi-frame counter for multi-frame data that operates according to the phase difference between input and output stored in the latch circuit 20.
22 is an output phase-synchronized multi-frame counter (multi-frame counter) that operates with an externally applied phase.
frame red multi-frame counter), 23a switching circuit that switches between the output of the multi-frame counter 21 for multi-frame system data and the output of the output phase-synchronized multi-frame counter n and outputs it to RAMI, 24U7 frame
A multi-frame counter for single-frame data that is reset at the same time as the multi-frame counter 21 is reset, and is incremented at the same time as the multi-frame phase of the increment frame wheel multi-frame counter 21; 25a single-frame data and multi-frame data; P, M2 who have accumulated the knowledge to distinguish between
Reference numeral 6 denotes a selection circuit which specifies the data to be replaced with data to be newly written to EAMl from among the output data of RAM1, using the multiframe phase output of the frame/multiframe counter 22, and uses the other data as the output data of tRAMl. , 27 is a selection circuit that selects between a single frame data selection signal and a multiframe data selection signal according to the output of the RAM 25, and 2a is a selection circuit that selects between single frame data and multiframe data according to the output of this selection circuit 2T. This is a selection circuit that selects.

FIG. 2 is a diagram showing the correspondence between memory addresses and multi-frame counters in the embodiment shown in FIG. 1, and FIG. 3 is a diagram showing memory input/output.
(a) is the operating clock φz, (e)
is the input data stream, (d) is the input address of F, M1, (@) is the read (READ)/write (wRx)
TE), 0) indicate data. FIG. 4 is a diagram showing the operation of the multi-frame counter 21 shown in FIG.
(d) shows the 1-bit delay in reception synchronization pattern detection, (e) shows the output of the latch circuit 20, and (f) shows the output of the multi-frame counter 21. .

Figure wc5 is a diagram showing the reception synchronization pattern to be detected by the comparator 19 in Figure 1.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIGS. 2 to 5. Here, a case of 20 multiframes will be explained.

First, in Figure 81, the 7 frame multi-frame counters 21 and 22 are composed of 20 x 193 = 3860 stage ring counters, of which the frame-multi-frame counter 220 bit phase corresponds to the pit of the desired output multi-frame. It's in phase. The frame fist multi-frame counter 21 is a ring collar with 20×193=3860 steps that can operate in any pit phase. The frame counter 16 is a 193-stage ring counter that takes an initial value of 0 when reset, and generates a carrier when the value reaches 192. Also, multi-frame counter 1
Reference numeral 7 is a 20-stage ring counter configured to take the initial value O when it is reset, and when it counts 20 and the count enable becomes significant, it generates a carrier which is a reference for multi-frames. That is, the frame counter 16 and the multi-frame counter 17 are combined to form a counter with 193×20=3860 stages.

The clock is the same for the input and output of the data stream, and there are 20 x 193 = 3860 multi-frame phases of the data stream. That is, there are 3860 different phase differences between the desired output multi-frame phase and the input multi-frame phase. R.A.
In MI, in order to absorb this phase difference, 193 words x
It requires a capacity of 20 bits to 3860 bits. FIG. 2 shows how this data is stored in the memory. The reason why one word is 20 bits is to simplify the operation of the comparator 19. The write address of the data stream to the RAMI is performed by the data line representing 0=192 of the 7-frame counter section output of the frame/multiframe counter 22 operating at the desired output phase. The writing bits of the data stream are selected by the selection circuit 26 using the data lines representing O to 19 of the output of the multi-frame counter section of the frame-multi-frame counter 22, and the data of the designated bit is replaced with new data. For remaining data that is not specified, the read data is written as is. In this way, it operates as if it were a 3860 word x 1 bit memory. In this case, it is 1 boat memory, so
Reading and writing must be performed within the operating cycle.

Therefore, as shown in FIG. 3, in order to operate as if writing to a 3860 word x 1 bit memory, the operating cycle is 374 I! Use the first period. The 20-bit data read for the above operation is output to the comparator 19. This comparator 19 temporarily holds the data of 20 bits read out in the 1/4 cycle until the data of the 4th cycle read out in the next operation cycle arrives. data and 5th rI
20 data obtained by rotating the multi-frame synchronization pattern as shown in ti are compared. I do this all the time. Then, the carrier pulse A from the multi-frame counter 17 is input to the comparator 19, and when the carrier pulse A and the comparison output pulse match, the coincidence pulse Ct and the carrier output pulse A are determined to be significant. Output at the appropriate timing. Further, when the carried pulse A and the comparison output pulse are not -1 or O, a mismatch pulse D is output at the timing when the carried pulse A becomes significant.

Here, first, when the synchronization is lost and the hunting state is entered, the synchronization butter/detection pulse B from the comparator 19 passes through the gate 18, which is opened by the hunting state signal E, to the 7-frame counter 16 and the multi-frame counter. 17
t-Reset. Then, each clock counts up. If the synchronization pattern detection pulse B does not arrive for one multiframe after a certain synchronization pattern detection pulse is loaded, the multiframe counter 17
The carrier output balsum is output from. If the last loaded synchronization pattern detection pulse B is the result of real synchronization pattern detection, the timing at which the out-of-pulse pulse A and the synchronization pattern detection pulse B become significant should coincide.

If these match, a match pulse C is output to the protection circuit 15 at the timing when the carrier out pulse becomes significant. Even if the last loaded carrier output pulse is due to a pseudo synchronization pattern, a carrier output pulse due to a real synchronization pattern will be generated within one multiframe, and the frame counter 1ε and multiple It should be loaded with the frame counter 11.

When the coincidence pulse C is input to the protection circuit 15, the backward protection counter therein counts up from "0" to "11", and the hunting state signal E becomes insignificant. Then, the gate 18 closes in response to the synchronization pattern detection pulse B and is no longer loaded. Then, the frame counter 16 and multi-frame counter IT operate as ring counters. At the same time, the forward protection counter is reset. Then, if the coincidence pulses C continue as many times as the number of backward protection stages, the synchronization state signal F becomes significant. Of course, if the mismatch pulse D is input between the coincidence pulse and the coincidence pulse, the backward protection counter will be reset and the synchronization will be restarted from the initial hunting state.

In addition, when the current synchronization phase changes due to data slip etc., the timing at which the carrier pulse ^ from the multi-frame counter 17 becomes significant does not match the synchronization pattern detection pulse B, so the comparator 19 detects a mismatch. Pulse D is output. If the mismatch pulses D2M continue for the number of forward protection stages, the synchronization state signal F becomes out of phase. Then, the hunting state signal E becomes significant under the AND condition of the out-of-synchronization state and the backward protection counter value of 0, and therefore enters the hunting state.

Then, the system returns to the synchronized state using the nine steps described above.

Next, the multi-frame alignment operation will be explained.

In the synchronized state, the phase in which the carried pulse A is significant is the first one of the multi-frame phases in the data stream.
Since this carrier pulse A becomes significant, the desired data stream output phase is memorized, and when the desired data stream output phase is at the beginning of the multi-frame, If the address of the phase next to the previously stored output phase is given to the RAM 1 and the data is read out, the data at the beginning of the desired multi-frame will be found among the data.

As shown in FIG. 4, the latch circuit 20 at the next timing after the carried pulse A becomes significant.
The phase of the 3860-stage frame/multiframe counter 22 operating at the desired multiframe phase is latched. G is a multi-frame pulse. Next, the frame multi-frame counter 21 is reset at the timing of the multi-7 frame pulse corresponding to the latched counter value. Then, in the switching circuit 23, the frame/multiframe counter 2 is set in the first half period of the data stream period.
It operates to select the frame phase output of No. 2 and the frame phase output of the frame/multiframe counter 21 in the second half period. By operating in this way, in the second half of the 1/4111 period, 20-bit data of mutually different multi-frame phases, which are only frame aligned, will be output simultaneously.

Now, multi-frame alignment for multi-frame data is specified by the multi-frame output of the frame cost multi-frame counter 21 and selects 9 bits from the 20-bit data output in the second half of the data cycle. It is done by

In addition, 7-frame alignment for single-frame data is performed when the multi-frame phase part of the 7-frame multi-frame counter 21 is set at an arbitrary multi-frame phase among the 20 bits output in the second half of the data cycle. Frame alignment is performed even if specified by a multi-frame counter output that increments at the same time.

However, when considering minimizing the delay time of single-frame data, it is difficult to select data with the same multi-frame phase as the multi-frame phase that is written in the first 3 or 4 cycles of the data cycle. Minimize time. Just to be sure, the change in multiframe phase is
This must be done at the same time as the change in the read-side multi-frame, which is carried out in the latter half of the data period 31, . . . '4.

As a precaution, the output of the multi-frame counter 24 is reset at the same time as the frame multi-frame counter 22 is reset, and is incremented by the carrier signal that appears when the frame phase of the frame multi-frame counter 21 reaches 192. By selecting the bit specified by , 7-frame alignment with the minimum delay time is performed.

Here, 1[, which identifies whether the data is single-frame type data or multi-frame type data stored in the RAM 25, is
Frame alignment with the minimum delay time is achieved by driving and selecting the output of the frame phase section of the frame multi-frame counter 22.

Here, information identifying whether the data is single 7 REM data or multi-frame data stored in the RAM 25 is driven by the output of the frame phase section of the frame/multi-frame color/receiver 22 and input to the selection circuit 2T. Therefore, the output of the multi-frame counter 24 is selected for single-frame data, and the output of the multi-frame phase portion of the frame-multi-frame counter 21 is selected for multi-frame data.

In this way, the output of the selection circuit 2T is
Nine bits are selected from the 20-bit memory output data according to single frame data or multi-frame data, and frame alignment and multi-frame alignment are performed.

In the above embodiment, multi-frame synchronization detection was performed using one set of counter resets for the frame color/return 16, multi-frame counter 17, and gate 1a, but multi-frame synchronization detection was performed using a 1-bit shift method of the counter. You may do so.

Furthermore, in the above embodiment, 1 bit is output from the 20-bit memory output.
To select bits, we first determined which multiframe phase the data was in depending on whether it was single frame data or not. Bit selection of frame data may be performed, and then single data selected as one bit and multiframe data may be selected depending on whether the data is single data or not.

〔Effect of the invention〕

As described above, the present invention is capable of performing multi-frame synchronization and multi-frame alignment for multi-frame data using one RAM, and by performing frame synchronization and frame alignment for single 7-frame data. Since the memory for multi-frame synchronization detection, memory for multi-frame alignment, and memory for 7-frame alignment are used together, the circuit size can be kept small, and the delay time can be minimized for TE and single frame data. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a multi-frame alignment circuit according to the present invention, FIG. 2 is a diagram showing the correspondence between memory addresses and multi-frame counters in the embodiment shown in FIG. 1, and FIG. Diagram showing the input and output of
The figure shows the operation of the frame/multiframe counter shown in Fig. 1, Fig. 5 shows the reception synchronization pattern to be detected by the comparator in Fig. 1, and Fig. 6 shows the conventional multiframe alignment circuit. A block diagram showing an example of
FIG. 7 is a frame configuration diagram used for reading the operation of FIG. 6. 1...RAM (random access memory), 16
6e Fist e Frame counter, l 7 e * s a Multi frame counter, 18-・Written・RAM (random access memory 9.19・φ・・Comparator, 20...
Latch circuit, 21.22・Work・Ring frame・Multi frame counter (Multi frame L/-mu counter), 23・
...Switching circuit, 24...+1@multi-frame counter, 25----RAM (random access memory),
27.28...Selection circuit.

Claims (1)

[Claims] Data in which a predetermined multi-frame synchronization pattern is distributed at regular intervals in a multi-frame consisting of a plurality of frames is received, and received input phase information is detected from the synchronization pattern in the received data by a multi-point monitoring method. ,
In a circuit that performs frame alignment for single-frame data and multi-frame alignment for multi-frame data based on the detected information, a first circuit having a capacity to store received data for at least one multi-frame is used. A random access memory, a comparator for detecting a synchronization pattern in the output sent from the first random access memory, and a multi-frame pulse whose received input phase is synchronized by being driven by the output of the comparator. A reception input phase-synchronized multi-frame counter to generate, a latch circuit that stores input-output phase difference information using the multi-frame pulse from this reception-input phase-synchronized multi-frame counter, and a latch circuit that stores input-output phase difference information stored in this latch circuit. a multi-frame counter for multi-frame data that operates accordingly;
A multi-frame counter for single-frame data, an output phase-synchronized multi-frame counter, an output of the multi-frame counter for multi-frame data, and an output of the output phase-synchronized multi-frame counter are switched between the first random access memory. a second random access memory that stores information for identifying single-frame data and multi-frame data; and a single-frame data selection signal in response to the output of the second random access memory. and a second selection circuit that selects between single frame data and multiframe data in accordance with the output of the first selection circuit. A multi-frame alignment circuit characterized by: