JPH0452506B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an analog integrator, and more particularly to an improvement in DC offset in the analog integrator.

[Technical background of the invention and its problems]

Generally, Miller integration, current integration, etc. are used in analog integration circuits. For example, FIG. 2 shows the basic configuration of a current integration type analog integration circuit.

The input is provided by a current source 1, the output current is time integrated, ie stored as a charge in a capacitor 2, and the output voltage is outputted through a buffer amplifier 3 to an output terminal.

However, in reality, analog circuits such as the buffer amplifier 3 essentially have a DC offset as shown in 4. The current source 5 models the current offset, and the voltage source 6 models the voltage offset. These DC offsets appear as calculation errors in the integrator output, so
A means to remove these offsets is required.

An example of an integrator equipped with such means is shown in FIG. This integrator has a configuration in which a selective feedback loop for correcting DC offset is added to the above configuration. That is, an error amplifier 7 is provided between the output terminal of the buffer amplifier 3 and the ground, a capacitor 8 that temporarily stores this output voltage, a buffer amplifier 9, and a buffer amplifier that receives the output of this amplifier 9 as a control voltage and changes the output current. Current source 10 input to the input of 3
It consists of Then, in the calibration mode, turn off the switch (SW1) between current source 1 and capacitor 2,
The switch (SW2) between the error amplifier 7 and the capacitor 8 is turned on, and when the input is zero, the output voltage is detected and fed back to the input so that the output becomes zero. Then switch (PW1) in operation mode.
Turn on the switch (SW2) and turn it off. Then, the output current of the current source 1 flows to the capacitor 2 and is integrated, while the input impedance of the buffer amplifier 9 is high and the switch (SW2) is off, so the output voltage of the capacitor 8 is maintained and the DC offset is removed. The operation for this purpose is also maintained.

However, with the above configuration, the DC offset removal circuit tends to become unstable in practice. That is,
A feedback loop is formed during calibration, and this loop includes capacitors 2 and 8 that have a time constant, and in reality, the error amplifier 7 also has a time constant.
Since there are three or more stages of time constant circuits in the loop, oscillation is likely to occur.

[Purpose of the invention]

The present invention has been made in view of the problems of conventional analog integrators as described above, and it is an object of the present invention to provide an analog integrator which can eliminate DC offset and is stable without oscillation.

[Summary of the invention]

The present invention includes: a first current source; a first switch connected to the current source; a first capacitor that stores the output current of the first current source when the switch is on; a first buffer amplifier for detecting voltage; an error amplifier connected between the output terminal of the buffer amplifier and ground; and an error amplifier connected to the output terminal of the error amplifier and turned on when the first switch is off. A second switch, a second capacitor provided between the other end of this switch and ground, a second buffer amplifier that detects the voltage of this capacitor, and an output voltage of this buffer amplifier that is applied to a control terminal. and a second current source, the first capacitor being connected between the input terminal of the first buffer amplifier and the control terminal of the second current source.

〔Effect of the invention〕

According to the present invention, since the first capacitor for integration is connected between the input terminal of the first buffer amplifier and the control terminal of the second current source, and the output impedance of the second buffer amplifier is low, In the operating mode in which the first switch is on and the second switch is off, the first capacitor has an integral action and the first
In the calibration mode, in which the first switch is off and the second switch is on, this capacitor acts as a compensation to advance the phase in the feedback loop. Therefore, there is an advantage that a stable analog integrator that is less likely to oscillate can be obtained.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIG. The circuit of this embodiment is almost the same as the conventional example shown in FIG. 3, except for the connection of the integrating capacitor. That is, a switch (SW11) is connected in series to the current source 11, and further connected to the input end of a capacitor 12 and a buffer amplifier 13, in which charge is accumulated when the switch is on. Note that 14 shown at the input of the buffer amplifier 13 indicates a DC offset, 15 indicates a current offset, and 16 indicates a voltage offset.

An error amplifier 17 is connected to the output terminal of the buffer amplifier 13.
The negative input terminal of is connected. The positive input terminal of this amplifier 17 is grounded, a switch (SW12) is connected in series to its output terminal, and the input terminal of a capacitor 18 and a buffer amplifier 19 are connected to the other end of this switch. The output terminal of buffer amplifier 19 is connected to the control input terminal of current source 20 , and the output terminal of current source 20 is connected to the input terminal of buffer amplifier 13 . The integration capacitor 12 is connected between the control input terminal of the current source 20 and the input terminal of the buffer amplifier 13.

Next, the operation of this circuit will be explained. First, in the calibration mode for removing the DC offset, the switch (SW11) is turned off and the switch (SW12) is turned on. The output impedance of the buffer amplifier 19 is very small and is almost equivalent to one end of the capacitor 12 being grounded. The switch (SW11) is off and the input is zero, but due to the existence of a DC offset, the output of the buffer amplifier 13 is not zero, but this output is inverted by the error amplifier 17 and sent to the buffer amplifier 19 via the switch (SW12). It is applied to the control input terminal of the through current source 20. The output current of the current source changes in accordance with this control input, so that the DC offset is removed. The output of the error amplifier 17 when the output of the buffer amplifier 13 becomes zero is stored in the capacitor 18 via the switch (SW12).

Next, in the operation mode, the switch (SW11) is turned on and the switch (SW12) is turned off. At this time, the output current of the current source 11 passes through the switch (SW11), is stored as a charge in the capacitor 12, and an integral operation is performed. Since the input impedance of the buffer amplifier 19 is high, the capacitor 18 is
This voltage is applied to the control input terminal of the current source 20 through the buffer amplifier 19, and the DC offset is removed. Therefore, the accurately integrated output voltage is passed through the buffer amplifier 13 and output.

According to this embodiment, the capacitor 2 is connected between the input terminal of the buffer amplifier 3 and the control input terminal of the current source 10, and in the calibration mode, the capacitor acts to advance the phase formed by the feedback loop, thereby causing an error. This will compensate for the phase delay in the amplifier. Therefore, it does not oscillate and becomes a stable analog integrator.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram explaining the principle of a current-integrating type analog integrator, and FIG. 3 is a block diagram of a conventional analog integrator. 11, 20... Current source, 12, 18... Capacitor, 13, 19... Buffer amplifier, 14... DC offset, 17... Error amplifier.

Claims (1)

[Claims] 1 A first current source, a first switch connected to this current source, a first capacitor that stores the output current of the first current source as a charge when the switch is on, and a first buffer amplifier for detecting voltage; an error amplifier connected between the output terminal of the buffer amplifier and ground; and an error amplifier connected to the output terminal of the error amplifier and turned on when the first switch is off. a second switch;
A second capacitor provided between the other end of this switch and ground, a second buffer amplifier that detects the voltage of this capacitor, and a second current source that applies the output voltage of this buffer amplifier to a control terminal. Equipped with
An analog integrator characterized in that the first capacitor is connected between the input terminal of the first buffer amplifier and the control terminal of the second current source.