JPH0456330A - Manufacture of mos type transistor - Google Patents

Abstract

PURPOSE:To prevent pinch off in this region, increase drive current, and improve the reliability with hot carrier by adopting the structure where a first source and drain regions are directly hidden under a gate and fail to exist outside a gate electrode definitely. CONSTITUTION:A gate oxide film 12 and a first gate electrode 1 are formed on a Si substrate 11, which are masked so that low concentration ions are implanted. After a first source 2/drain region is prepared, a second gate electrode 4 is deposited. A side wall 5 is formed by an insulation film on the side of the first gate electrode 1 where high concentration ions are implanted with the first gate electrode 1 and the first side wall 5 as a mask, thereby forming second source 6/drain regions 7. Then, a second side wall 10 is formed again by an insulation film on the side of the first side wall 5. A second gate electrode 4 exposed on the surface is etched, which creates the construction under which the first source 2/drain regions 3 are hidden under the gate and they never exist outside the gate electrode. It is also acceptable to form a contact region which adjoins with the source 6/drain 7 regions.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention (i.e., a MOS transistor with high speed and high reliability by covering most of the source and drain with a gate electrode)
Related to the manufacturing method of type transistors.Conventional technology DEVICE, Vol. ED-29, No. 4. April
After forming the gate electrode 22 on the gate oxide film 21 of the semiconductor substrate 20 (a), low concentration ion implantation is performed using the gate electrode 22 as a mask. Line (\ 1st source 2
3 and drain 24 regions b), and then sidewalls 25 are formed on the side surfaces of the gate electrode 22 using an insulating film; c), by performing high-concentration ion implantation using the gate electrode 22 and sidewalls 25 as masks. forming second source 26 and drain 27 regions; d)
, after etching the gate oxide film 21 exposed on the surface, depositing A1 or the like on part or all of the second source 26 and drain 27 to form a contact e),
L D D (Lightly Doped Drai
By this method, it is possible to form a MOS transistor with high reliability in terms of drain breakdown voltage and the like.

Problems to be Solved by the Invention A MOS transistor with an LDD structure (i) A structure in which the LDD region plays the role of alleviating the drain electric field and provides high reliability in terms of drain breakdown voltage, etc. Generally, most of the LDD region is not directly under the gate electrode, but is directly below the gate electrode. Tatori located on the outside
The LDD region located outside the gate electrode tends to pinch off and become a high resistance layer.As a result, compared to a conventional single source/drain structure MOS transistor, the LD
D-structure MO3O3 transistor has the following drawbacks: 1. Drive current decreases due to the presence of the high resistance layer in series; 2. Hot electrons are injected into the sidewall, causing The n-layer directly below pinches off and becomes extremely high in resistance. All conventional single source/drain structure MOS transistors,
The drive current is significantly degraded by hot electrons, creating a major reliability problem.

The present invention solves the above problems while maintaining high reliability in the MO3O3 transistor line breakdown voltage of the conventional LDD structure, and can realize a device having both high performance and high reliability.

The present invention is a means to solve the problem! Friend: In order to solve the above problems, the first gate electrode is formed on the gate insulating film formed in the MOS type transistor region on the surface of the semiconductor substrate, and the first gate electrode is used as a mask to form a first gate electrode on the semiconductor substrate. forming first source and drain regions by ion implantation into the surface; depositing a second gate electrode again; and depositing the second gate electrode on the first gate electrode and its side surfaces. forming a first insulating film so as to cover the side surfaces of the insulating film, and implanting ions at a higher concentration than the ion implantation into the first source and drain regions using the gate electrode whose side faces are covered with the insulating film as a mask. forming second source and drain regions by covering the first gate electrode and the second insulating film deposited on the side surfaces of the first gate electrode; A method for manufacturing a MOS transistor, which includes a step of forming a second insulating film that overlaps most of the second source and drain, and a step of etching the second gate electrode using the second insulating film as a mask. SUMMARY OF THE INVENTION The present invention provides a method for forming contact portions adjacent to the source and drain in Table 2.

Operation The present invention provides a structure in which the first source and drain regions are hidden directly under the gate and never exist outside the gate electrode.

Since the first source and drain regions are not pinched off, it is possible to realize a MOS transistor with a large drive current and high reliability against hot carriers.

Example (Example 1) Figures 1 and 2 (respectively show examples of the present invention)
It shows the structure and manufacturing method when applied to a DD structure MOS transistor.

As shown in FIG. 1, an inverted T-shaped gate crossing channel region 13 consisting of a gate electrode 1 and a gate electrode 4. It covers most of the first source 2/drain 3 region and a part of the second source 5/drain 6, and even if contact is made adjacent to the second source 5/drain 6, the An example of the manufacturing method in this example is shown.

a) For example, P-ty with an impurity concentration of ~IE16cm-"
A gate oxide film 12 (Sin
s, film thickness 10-20 nm)
The first gate electrode 1 (gate length 0.6 to 0
．． Using the first gate electrode 1 as a mask, low concentration ion implantation (P or As, 20 to 60 μm) is performed.
b) Depositing the second gate electrode 4 of Po1ySi. At this time, the first gate electrode 1 becomes larger because n''PolySi is deposited on its upper and side surfaces.

C) A first sidewall 5 (sidewall length 200 nm) is formed on the side surface of the first gate electrode 1 using an insulating film, and high concentration ion implantation (P or As, 20
~60 KeV, IEI 5 ~ IE16 cm-'') to form a second source 6/drain 7 region.

d) Again, a second sidewall 10 (sidewall length 200 nm) is formed on the side surface of the first sidewall 5 using an insulating film.
) and etching the n''PolySi exposed on the surface.
The low-concentration region of the source 2/drain 3 (hidden directly under the gate and never exists outside the gate electrode can be obtained).The low-concentration region of the first source 2/drain 3 does not pinch off, so the driving A MOS transistor with a large current and high reliability against hot carriers can be obtained (Example 2) 1) Example 1 (a) to (b) are carried out.

2) Example 1 (c) A contact region 8 is provided in a region adjacent to the second source 6/drain 7 (for example, the position shown in FIG. 1), and high concentration ions are implanted into the contact region 8. I also do it.

3) Perform Example 1 (d).

4) A contact is formed by depositing AI or the like on a part or all of the fine contact region 8 that has been etched on the gate oxide film 12 exposed on the surface. Although the margin increases, the transistor in these embodiments may be a P channel instead of an N channel (℃, or the transistor may be a MIS using a nitride film instead of an oxide film) or a Run sister. Furthermore, this structure may be applied to only one side of the source/drain (℃) As described in detail, the present invention retains advantages over the conventional LDD structure such as MOS type transistor and drain breakdown voltage. It should improve the shortcomings such as the drop in drive current due to pinch-off of the L and n-layers.It should be possible to obtain a MOS transistor with high performance and high reliability.The practical effects are significant.

[Brief explanation of the drawing]

FIGS. 1(a) and 2(b) are a plan view of an N-channel MO8 type transistor according to an embodiment of the present invention viewed from above, and an i-i line disconnection plate; FIGS. 2(a) to (d) are Process cross-section of the manufacturing method of the N-channel MO8 type transistor in the example @ Fig. 3 (a) to (e) are the conventional LD
This is a cross-sectional diagram of the process for manufacturing a D-structure MOS transistor. 1st... 11th? -Toden Kaede 2... 1st Sojin 3... 1st Doreshin, 4... 2nd +'-) Electrode 5 ・ ・ ・ 1st Cybiraor, 6 ・
・ 2nd source 7 ・ ・ 2nd drain 10 ・ ・ 2nd Cybi wall 11 .

Claims (2)

[Claims] (1) A step of forming a first gate electrode on a gate insulating film formed on a portion of the surface of the semiconductor substrate that will become a MOS type transistor region, and implanting ions into the surface of the semiconductor substrate using the first gate electrode as a mask. forming first source and drain regions; depositing a second gate electrode again; forming a first insulating film on the first source and drain regions; and using the gate electrode whose side surfaces are covered with an insulating film as a mask, the second source is implanted at a higher concentration than the ion implantation into the first source and drain regions. and a step of forming a drain region, covering the first gate electrode and the second gate electrode and the first insulating film deposited on the side surfaces of the first gate electrode and forming the second source and drain regions. M characterized by comprising the steps of forming a second insulating film that overlaps most of the drain, and etching the second gate electrode using the second insulating film as a mask.
A method of manufacturing an OS type transistor. (2) The M according to claim (1), wherein the contact portion is formed adjacent to the second source and drain.
Manufacturing method of OS type transistor