JPH0457924U - - Google Patents
Info
- Publication number
- JPH0457924U JPH0457924U JP10033790U JP10033790U JPH0457924U JP H0457924 U JPH0457924 U JP H0457924U JP 10033790 U JP10033790 U JP 10033790U JP 10033790 U JP10033790 U JP 10033790U JP H0457924 U JPH0457924 U JP H0457924U
- Authority
- JP
- Japan
- Prior art keywords
- input control
- control clock
- output terminal
- channel transistor
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Logic Circuits (AREA)
Description
第１図は本考案の出力バツフア回路を示す回路
図、第２図は第１図に示した出力バツフア回路の
出力電圧波形図、第３図は従来の出力バツフア回
路を示す回路図、第４図は第３図に示した出力バ
ツフア回路の出力電圧波形図である。
Ｍ１，Ｍ２，Ｍ３……Ｎチヤンネルトランジス
タ、ＶＣＣ……電源電圧、ＶＳＳ……接地電圧、
Ｄｏｕｔ……出力端子、φ，，φ＋……入力制
御クロツク、Ｖｏｕｔ，Ｖ′ｏｕｔ……出力電圧
、Ｖｔ……しきい値電圧。
Fig. 1 is a circuit diagram showing the output buffer circuit of the present invention, Fig. 2 is an output voltage waveform diagram of the output buffer circuit shown in Fig. 1, Fig. 3 is a circuit diagram showing a conventional output buffer circuit, and Fig. 4 is a circuit diagram showing the output buffer circuit of the present invention. This figure is an output voltage waveform diagram of the output buffer circuit shown in FIG. 3. M 1 , M 2 , M 3 ... N channel transistor, VCC ... power supply voltage, VSS ... ground voltage,
Dout...output terminal, φ,,φ + ...input control clock, Vout, V'out...output voltage, Vt...threshold voltage.
Claims (1)
、第２のＮチヤンネルトランジスタと、 前記第１、第２のＮチヤンネルトランジスタの
ゲートに接続される共通の入力制御クロツクをい
ずれか一方のゲートについて昇圧するための昇圧
手段と、 前記出力端子と接地電圧の間に接続され、ゲー
トに前記入力制御クロツクを反転した入力制御ク
ロツクが接続された第３のＮチヤンネルトランジ
スタとを具備することを特徴とする出力バツフア
回路。[Claims for utility model registration] The first battery connected in parallel between the power supply voltage and the output terminal
, a second N-channel transistor, boosting means for boosting a common input control clock connected to the gates of the first and second N-channel transistors for either gate, and the output terminal and ground. and a third N-channel transistor connected between voltages and having a gate connected to an input control clock that is an inversion of the input control clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10033790U JPH0457924U (en) | 1990-09-25 | 1990-09-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10033790U JPH0457924U (en) | 1990-09-25 | 1990-09-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0457924U true JPH0457924U (en) | 1992-05-19 |
Family
ID=31842911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10033790U Pending JPH0457924U (en) | 1990-09-25 | 1990-09-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0457924U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6083419A (en) * | 1983-10-13 | 1985-05-11 | Nec Corp | Output buffer circuit |
| JPH02230818A (en) * | 1988-11-25 | 1990-09-13 | Mitsubishi Electric Corp | Output circuit for semiconductor device |
-
1990
- 1990-09-25 JP JP10033790U patent/JPH0457924U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6083419A (en) * | 1983-10-13 | 1985-05-11 | Nec Corp | Output buffer circuit |
| JPH02230818A (en) * | 1988-11-25 | 1990-09-13 | Mitsubishi Electric Corp | Output circuit for semiconductor device |
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