JPH0472627U - - Google Patents

Info

Publication number
JPH0472627U
JPH0472627U JP1990115841U JP11584190U JPH0472627U JP H0472627 U JPH0472627 U JP H0472627U JP 1990115841 U JP1990115841 U JP 1990115841U JP 11584190 U JP11584190 U JP 11584190U JP H0472627 U JPH0472627 U JP H0472627U
Authority
JP
Japan
Prior art keywords
semiconductor chip
wire bonding
widened
pads
corners
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990115841U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990115841U priority Critical patent/JPH0472627U/ja
Publication of JPH0472627U publication Critical patent/JPH0472627U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例による半導体チツ
プを示す構成図、第２図は従来の半導体チツプの
構成図である。 図において、１は半導体チツプ、２はワイヤボ
ンデイングするためのパツド、３はパツケージの
インナーリード、４は半導体チツプのパツドとパ
ツケージのインナーリードを接続するワイヤ、Ｓ
１〜Ｓ３はパツドの間隔である。なお図中、同一
符号は同一又は相当部分を示す。 FIG. 1 is a block diagram showing a semiconductor chip according to an embodiment of this invention, and FIG. 2 is a block diagram of a conventional semiconductor chip. In the figure, 1 is a semiconductor chip, 2 is a pad for wire bonding, 3 is an inner lead of the package, 4 is a wire connecting the pad of the semiconductor chip and the inner lead of the package, S
1 to S3 are pad spacings. In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体チツプのワイヤボンデイング用のパツド
の間隔を、該半導体チツプのコーナーに近づくに
つれて広げたことを特徴とする半導体装置。 A semiconductor device characterized in that the spacing between pads for wire bonding on a semiconductor chip is widened as the distance approaches the corners of the semiconductor chip.
JP1990115841U 1990-10-31 1990-10-31 Pending JPH0472627U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990115841U JPH0472627U (en) 1990-10-31 1990-10-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990115841U JPH0472627U (en) 1990-10-31 1990-10-31

Publications (1)

Publication Number Publication Date
JPH0472627U true JPH0472627U (en) 1992-06-26

Family

ID=31863644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990115841U Pending JPH0472627U (en) 1990-10-31 1990-10-31

Country Status (1)

Country Link
JP (1) JPH0472627U (en)

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