JPH048433U - - Google Patents
Info
- Publication number
- JPH048433U JPH048433U JP1990049302U JP4930290U JPH048433U JP H048433 U JPH048433 U JP H048433U JP 1990049302 U JP1990049302 U JP 1990049302U JP 4930290 U JP4930290 U JP 4930290U JP H048433 U JPH048433 U JP H048433U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- package
- view
- plan
- die bond
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
Landscapes
- Wire Bonding (AREA)
Description
第１図および第２図はこの考案の一実施例を示
す図で、第１図は平面図、第２図は要部破断平面
図、第３図はこの考案の他の実施例を示す要部破
断平面図、第４図はこの考案の他の実施例を示す
平面図、第５図および第６図は従来のこの種半導
体装置を示す図で、第５図は平面図、第６図は要
部破断平面図である。
図中、１はＩＣパツケージ、２は半導体チツプ
、３はダイボンドエリア、４はリードフレーム、
５は金属細線である。なお、図中同一符号は同一
又は相当部分を示す。
Figures 1 and 2 are views showing one embodiment of this invention, in which Figure 1 is a plan view, Figure 2 is a plan view with a main part broken away, and Figure 3 is a schematic diagram showing another embodiment of this invention. 4 is a plan view showing another embodiment of this invention; FIGS. 5 and 6 are views showing conventional semiconductor devices of this type; FIG. 5 is a plan view, and FIG. is a fragmentary plan view of the main part. In the figure, 1 is an IC package, 2 is a semiconductor chip, 3 is a die bond area, 4 is a lead frame,
5 is a thin metal wire. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
この半導体チツプを被覆するパツケージを備え、
上記半導体チツプはこれの各辺が上記パツケージ
のいずれの一辺とも平行にならないように配置さ
れている半導体装置。 Semiconductor chip fixed to die bond area,
Equipped with a package that covers this semiconductor chip,
A semiconductor device in which the semiconductor chip is arranged such that each side of the semiconductor chip is not parallel to any one side of the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990049302U JPH048433U (en) | 1990-05-11 | 1990-05-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990049302U JPH048433U (en) | 1990-05-11 | 1990-05-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH048433U true JPH048433U (en) | 1992-01-27 |
Family
ID=31566870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990049302U Pending JPH048433U (en) | 1990-05-11 | 1990-05-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH048433U (en) |
-
1990
- 1990-05-11 JP JP1990049302U patent/JPH048433U/ja active Pending