JPH0451153U - - Google Patents
Info
- Publication number
- JPH0451153U JPH0451153U JP1990092849U JP9284990U JPH0451153U JP H0451153 U JPH0451153 U JP H0451153U JP 1990092849 U JP1990092849 U JP 1990092849U JP 9284990 U JP9284990 U JP 9284990U JP H0451153 U JPH0451153 U JP H0451153U
- Authority
- JP
- Japan
- Prior art keywords
- chips
- chip
- semiconductor device
- same
- packaged
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
Description
第１図はこの考案の一実施例による半導体装置
の断面図、第２図は第１図の上面図、第３図は従
来の半導体装置の断面図である。
図において、１，２は第１、第２のＩＣチツプ
、３は金属ワイヤ、４は内部リード、５は外部リ
ード、６はモールドパツケージ、７は接続部分、
７ａ，７ｂは接続部、８はパツド、１０はダイパ
ツドである。なお図中同一符号は同一又は相当部
分を示す。
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of this invention, FIG. 2 is a top view of FIG. 1, and FIG. 3 is a sectional view of a conventional semiconductor device. In the figure, 1 and 2 are first and second IC chips, 3 is a metal wire, 4 is an internal lead, 5 is an external lead, 6 is a molded package, 7 is a connecting part,
7a and 7b are connection parts, 8 is a pad, and 10 is a die pad. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
ム上にアセンブリし、 該第１のＩＣチツプ上に、これと同一あるいは
異なる機能を有する第２のＩＣチツプを両チツプ
間で相互に信号の入出力可能に搭載し、 上記両ＩＣチツプ全体をパツケージングしてな
ることを特徴とする半導体装置。[Claims for Utility Model Registration] A first IC chip having a predetermined function is assembled on a frame, and a second IC chip having the same or different function is mounted on the first IC chip. What is claimed is: 1. A semiconductor device, characterized in that both IC chips are mounted so that signals can be mutually input and output between the IC chips, and that both of the above IC chips are packaged as a whole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990092849U JPH0451153U (en) | 1990-09-03 | 1990-09-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990092849U JPH0451153U (en) | 1990-09-03 | 1990-09-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0451153U true JPH0451153U (en) | 1992-04-30 |
Family
ID=31829620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990092849U Pending JPH0451153U (en) | 1990-09-03 | 1990-09-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0451153U (en) |
-
1990
- 1990-09-03 JP JP1990092849U patent/JPH0451153U/ja active Pending