JPH0475542B2 - - Google Patents

Info

Publication number
JPH0475542B2
JPH0475542B2 JP59164719A JP16471984A JPH0475542B2 JP H0475542 B2 JPH0475542 B2 JP H0475542B2 JP 59164719 A JP59164719 A JP 59164719A JP 16471984 A JP16471984 A JP 16471984A JP H0475542 B2 JPH0475542 B2 JP H0475542B2
Authority
JP
Japan
Prior art keywords
circuit means
logic circuit
evaluation
pseudo
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59164719A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60105042A (ja
Inventor
Esu Tabusu Gurahamu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPS60105042A publication Critical patent/JPS60105042A/ja
Publication of JPH0475542B2 publication Critical patent/JPH0475542B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
JP59164719A 1983-08-05 1984-08-06 マルチレベル論理回路 Granted JPS60105042A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US52088083A 1983-08-05 1983-08-05
US520880 1983-10-03
US538634 1983-10-03

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP4142943A Division JPH0738155B2 (ja) 1983-08-05 1992-06-03 ディジタル乗算実行方法および装置

Publications (2)

Publication Number Publication Date
JPS60105042A JPS60105042A (ja) 1985-06-10
JPH0475542B2 true JPH0475542B2 (fr) 1992-12-01

Family

ID=24074430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59164719A Granted JPS60105042A (ja) 1983-08-05 1984-08-06 マルチレベル論理回路

Country Status (1)

Country Link
JP (1) JPS60105042A (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920006323B1 (ko) * 1990-05-31 1992-08-03 삼성전자 주식회사 스킵(Skip)배열과 수정형 월리스(Wallace)트리를 사용하는 병렬 승산기

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58153571A (ja) * 1982-03-09 1983-09-12 三菱化工機株式会社 沈積スラツジ拡散装置
JPS6045842A (ja) * 1983-08-23 1985-03-12 Matsushita Electric Ind Co Ltd 乗算回路

Also Published As

Publication number Publication date
JPS60105042A (ja) 1985-06-10

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term