JPH0477342B2 - - Google Patents

Info

Publication number
JPH0477342B2
JPH0477342B2 JP21613783A JP21613783A JPH0477342B2 JP H0477342 B2 JPH0477342 B2 JP H0477342B2 JP 21613783 A JP21613783 A JP 21613783A JP 21613783 A JP21613783 A JP 21613783A JP H0477342 B2 JPH0477342 B2 JP H0477342B2
Authority
JP
Japan
Prior art keywords
request
memory
stack
memory device
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP21613783A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60108941A (ja
Inventor
Akira Ishama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP21613783A priority Critical patent/JPS60108941A/ja
Publication of JPS60108941A publication Critical patent/JPS60108941A/ja
Publication of JPH0477342B2 publication Critical patent/JPH0477342B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP21613783A 1983-11-18 1983-11-18 メモリインタフエ−ス回路 Granted JPS60108941A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21613783A JPS60108941A (ja) 1983-11-18 1983-11-18 メモリインタフエ−ス回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21613783A JPS60108941A (ja) 1983-11-18 1983-11-18 メモリインタフエ−ス回路

Publications (2)

Publication Number Publication Date
JPS60108941A JPS60108941A (ja) 1985-06-14
JPH0477342B2 true JPH0477342B2 (fr) 1992-12-08

Family

ID=16683842

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21613783A Granted JPS60108941A (ja) 1983-11-18 1983-11-18 メモリインタフエ−ス回路

Country Status (1)

Country Link
JP (1) JPS60108941A (fr)

Also Published As

Publication number Publication date
JPS60108941A (ja) 1985-06-14

Similar Documents

Publication Publication Date Title
EP0523764A2 (fr) Système d'ordinateur muni d'une interconnection directe parbus entre le processeur et la mémoire principale dynamique et d'une commande DMA incorporée au processeur, pour une pluralité de moyens d'échange de données égalament raccordés audit bus, et processeur central destiné à être utilisé dans un tel système d'ordinateur
EP0384620A2 (fr) Système de mémoire à haute performance
US4347567A (en) Computer system apparatus for improving access to memory by deferring write operations
JPS6297036A (ja) 計算機システム
JPH0479026B2 (fr)
JPH03189843A (ja) データ処理システムおよび方法
TW491970B (en) Page collector for improving performance of a memory
JPH0477342B2 (fr)
JPH0283736A (ja) バッファ記憶制御装置のｏｓｃ検出方式
JPS6191740A (ja) メモリ・アクセス制御方式
JP2574821B2 (ja) ダイレクトメモリアクセス・コントローラ
JPS6326753A (ja) メモリ−バス制御方法
JPS6079445A (ja) 記憶制御装置
JP2581144B2 (ja) バス制御装置
JPS616746A (ja) 部分書込み制御方式
JPS5890227A (ja) デ−タ転送インタ−フエイス方式
JPH04333950A (ja) 情報処理システム
JPH05120211A (ja) データバス幅制御装置
JPS5856891B2 (ja) 情報処理システム
JPH0652516B2 (ja) バス・インターフェース装置
JPH03228163A (ja) データ転送装置
JPS63239549A (ja) デ−タ・チエイニング制御方式
JPH0215095B2 (fr)
JPH01114961A (ja) ダイレクトメモリアクセス制御装置
JPH0690711B2 (ja) メモリアクセス制御方式