JPH0482731U - - Google Patents
Info
- Publication number
- JPH0482731U JPH0482731U JP12380690U JP12380690U JPH0482731U JP H0482731 U JPH0482731 U JP H0482731U JP 12380690 U JP12380690 U JP 12380690U JP 12380690 U JP12380690 U JP 12380690U JP H0482731 U JPH0482731 U JP H0482731U
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- registered
- pattern memory
- combinational logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Storage Device Security (AREA)
Description
第１図及び第２図はこの考案の一実施例を示す
図であり、第１図は出力パターンメモリの構成図
、第２図は登録パターンの状態を示す図、第３図
は従来の出力制御回路を示す図である。
１は計算機、２はデータバス、３はアドレスバ
ス、５ａは出力回路、６はアドレスデコーダ、８
は出力保護回路、１１は出力パターンメモリ、１
２は書き込み制御信号、１３はゲート回路、１４
は出力セレクト信号である。なお、図中、同一符
号は同一、又は相当部分を示す。
1 and 2 are diagrams showing an embodiment of this invention. FIG. 1 is a configuration diagram of an output pattern memory, FIG. 2 is a diagram showing the state of registered patterns, and FIG. 3 is a diagram showing a conventional output pattern memory. FIG. 3 is a diagram showing a control circuit. 1 is a computer, 2 is a data bus, 3 is an address bus, 5a is an output circuit, 6 is an address decoder, 8
is an output protection circuit, 11 is an output pattern memory, 1
2 is a write control signal, 13 is a gate circuit, 14
is the output select signal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
計算機、複数の制御装置を組合わせて使用するた
めの論理演算結果を外部の制御装置に出力する出
力回路、出力できる組合わせ論理データを予め登
録し、出力された組合わせ論理データが登録され
たデータか否かを判定する出力パターンメモリ、
出力回路と出力パターンメモリ計算機から出力さ
れたアドレス情報に従つて選択するアドレスデコ
ーダ、計算機から出力された組合わせ論理データ
が出力パターンメモリによつて判定され、登録さ
れている時はアドレスデコーダからのセレクト信
号を出力回路に転送し、もし未登録の時はセレク
ト信号を禁止するゲート回路より構成され、計算
機から出力回路へ組合わせ論理データの書き込み
が行われた場合、先ず出力パターンメモリで登録
パターンか否かをチエツクし、登録パターンであ
る場合は出力パターンメモリよりゲート回路に出
力可の信号を出力して出力回路にセレクト信号を
転送し、もし登録パターンでなかつた場合は出力
パターンメモリよりゲート回路にセレクト信号の
禁止を出力することによつて、出力回路への誤つ
た組合わせ論理データの出力を防止できることを
特徴とする出力制御回路。 A computer that executes calculations according to the program execution procedure, an output circuit that outputs logical operation results to an external control device for use in combination with multiple control devices, and combinational logic data that can be output are registered in advance. an output pattern memory that determines whether the output combinational logic data is registered data;
Output circuit and output pattern memory The address decoder selects according to the address information output from the computer, and when the combinational logic data output from the computer is determined by the output pattern memory and registered, the output from the address decoder is It is composed of a gate circuit that transfers the select signal to the output circuit and inhibits the select signal if it is not registered.When writing combinational logic data from the computer to the output circuit, first the registered pattern is written in the output pattern memory. If it is a registered pattern, it outputs an output enable signal from the output pattern memory to the gate circuit and transfers a select signal to the output circuit, and if it is not a registered pattern, it outputs a signal from the output pattern memory to the gate circuit. An output control circuit characterized in that outputting erroneous combinational logic data to an output circuit can be prevented by outputting a prohibition of a select signal to the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12380690U JPH0482731U (en) | 1990-11-26 | 1990-11-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12380690U JPH0482731U (en) | 1990-11-26 | 1990-11-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0482731U true JPH0482731U (en) | 1992-07-17 |
Family
ID=31871492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12380690U Pending JPH0482731U (en) | 1990-11-26 | 1990-11-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0482731U (en) |
-
1990
- 1990-11-26 JP JP12380690U patent/JPH0482731U/ja active Pending
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