JPH0486942U

JPH0486942U -

Info

Publication number: JPH0486942U
Application number: JP12843490U
Authority: JP
Priority date: 1990-11-30
Filing date: 1990-11-30
Publication date: 1992-07-28

Description

[Brief explanation of the drawing]

第１図及び第２図はこの考案の一実施例を示す
図であり、第１図は出力パターンメモリの構成図
、第２図は登録パターンの状態を示す図、第３図
は従来の出力制御回路を示す図である。１は計算機、２はデータバス、３はアドレスバ
ス、５ａは出力回路、６はアドレスデコーダ、８
は出力保護回路、１１は出力パターンメモリ、１
２は書き込み制御信号、１３はゲート回路、１４
は出力セレクト信号、１５は誤データ保持回路、
１６はエラー通報信号である。なお、図中、同一
符号は同一、又は相当部分を示す。 1 and 2 are diagrams showing an embodiment of this invention. FIG. 1 is a configuration diagram of an output pattern memory, FIG. 2 is a diagram showing the state of registered patterns, and FIG. 3 is a diagram showing a conventional output pattern memory. FIG. 3 is a diagram showing a control circuit. 1 is a computer, 2 is a data bus, 3 is an address bus, 5a is an output circuit, 6 is an address decoder, 8
is an output protection circuit, 11 is an output pattern memory, 1
2 is a write control signal, 13 is a gate circuit, 14
is an output select signal, 15 is an erroneous data holding circuit,
16 is an error notification signal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims

[Scope of utility model registration request]

A computer that executes calculations according to the program execution procedure, an output circuit that outputs logical operation results to an external control device for use in combination with multiple control devices, and combinational logic data that can be output are registered in advance. an output pattern memory that determines whether the output combinational logic data is registered data;
An address decoder selects the output circuit and output pattern memory according to the address information output from the computer, and when the combinational logic data output from the computer is determined by the output pattern memory and registered, the address decoder selects the output circuit and output pattern memory according to the address information output from the computer. It consists of a gate circuit that transfers the select signal to the output circuit, inhibits the select signal if it is unregistered, and an error data holding circuit that holds the unregistered combinational logic data when it is unregistered, and outputs from the computer. When combinatorial logic data is written to the circuit,
First, check the output pattern memory to see if it is a registered pattern, and if it is a registered pattern, output an output enable signal from the output pattern memory to the gate circuit and transfer a select signal to the output circuit, and if it is an unregistered pattern. outputs a prohibition of the select signal from the output pattern memory to the gate circuit, outputs a holding signal to hold the unregistered combinational logic data to the erroneous data holding circuit, and also sends an error report to the computer, thereby preventing the output circuit. An output control circuit characterized in that it can prevent the output of erroneous combinational logic data to a computer, and it can also cause a computer to read unregistered combinational logic data by means of an error notification signal.