JPH0482730U - - Google Patents
Info
- Publication number
- JPH0482730U JPH0482730U JP12380590U JP12380590U JPH0482730U JP H0482730 U JPH0482730 U JP H0482730U JP 12380590 U JP12380590 U JP 12380590U JP 12380590 U JP12380590 U JP 12380590U JP H0482730 U JPH0482730 U JP H0482730U
- Authority
- JP
- Japan
- Prior art keywords
- output
- registered
- circuit
- computer
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Storage Device Security (AREA)
Description
第１図及び第２図はこの考案の一実施例を示す
図であり、第１図は出力パターンメモリの構成図
、第２図は登録パターンの状態を示す図、第３図
は従来の出力制御回路を示す図である。
１は計算機、２はデータバス、３はアドレスバ
ス、５ａは出力回路、６はアドレスデコーダ、８
は出力保護回路、１１は出力パターンメモリ、１
２は書き込み制御信号、１３はゲート回路、１４
はラツチ信号である。なお、図中、同一符号は同
一、又は相当部分を示す。
1 and 2 are diagrams showing an embodiment of this invention. FIG. 1 is a configuration diagram of an output pattern memory, FIG. 2 is a diagram showing the state of registered patterns, and FIG. 3 is a diagram showing a conventional output pattern memory. FIG. 3 is a diagram showing a control circuit. 1 is a computer, 2 is a data bus, 3 is an address bus, 5a is an output circuit, 6 is an address decoder, 8
is an output protection circuit, 11 is an output pattern memory, 1
2 is a write control signal, 13 is a gate circuit, 14
is a latch signal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
計算機、複数の制御装置を組合わせて使用するた
めの論理演算結果を外部の制御装置に出力する出
力回路、出力できる組合わせ論理データを予め登
録し、出力された組合わせ論理データが登録され
たデータか否かを判定する出力パターンメモリ、
出力回路と出力パターンメモリを計算機から出力
されたアドレス情報に従つて選択するアドレスデ
コーダ、計算機から出力された組合わせ論理デー
タが出力パターンメモリによつて判定され、登録
されている時は計算機からの書き込み信号を出力
回路に転送し、もし未登録の時は書き込み信号を
禁止するゲート回路より構成され、計算機から出
力回路へ組合わせ論理データの書き込みが行われ
た場合、先ず出力パターンメモリで登録パターン
か否かをチエツクし、登録パターンである場合は
出力パターンメモリよりゲート回路に出力可の信
号を出力して出力回路に書き込み信号を転送し、
もし登録パターンでなかつた場合は出力パターン
メモリよりゲート回路に書き込み信号の禁止を出
力することによつて、出力回路への誤つた組合わ
せ論理データの出力を防止できることを特徴とす
る出力制御回路。 A computer that executes calculations according to the program execution procedure, an output circuit that outputs logical operation results to an external control device for use in combination with multiple control devices, and combinational logic data that can be output are registered in advance. an output pattern memory that determines whether the output combinational logic data is registered data;
An address decoder selects the output circuit and output pattern memory according to the address information output from the computer, and when the combinational logic data output from the computer is determined by the output pattern memory and registered, the output from the computer is It is composed of a gate circuit that transfers the write signal to the output circuit and prohibits the write signal if it is not registered.When writing combinatorial logic data from the computer to the output circuit, the registered pattern is first stored in the output pattern memory. If it is a registered pattern, the output pattern memory outputs an output enable signal to the gate circuit and transfers the write signal to the output circuit.
If the pattern is not a registered pattern, the output control circuit is capable of preventing the output of erroneous combinational logic data to the output circuit by outputting a write signal prohibition from the output pattern memory to the gate circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12380590U JPH0482730U (en) | 1990-11-26 | 1990-11-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12380590U JPH0482730U (en) | 1990-11-26 | 1990-11-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0482730U true JPH0482730U (en) | 1992-07-17 |
Family
ID=31871491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12380590U Pending JPH0482730U (en) | 1990-11-26 | 1990-11-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0482730U (en) |
-
1990
- 1990-11-26 JP JP12380590U patent/JPH0482730U/ja active Pending
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