JPH048432U - - Google Patents
Info
- Publication number
- JPH048432U JPH048432U JP1990048734U JP4873490U JPH048432U JP H048432 U JPH048432 U JP H048432U JP 1990048734 U JP1990048734 U JP 1990048734U JP 4873490 U JP4873490 U JP 4873490U JP H048432 U JPH048432 U JP H048432U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- bonding
- range
- chip
- effective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
Landscapes
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図〜第３図は本考案を表わしたＢパターン
の一部の拡大平面図、第４図は従来例を模式的に
表わした従来例の一部平面図、第５図は従来例の
欠陥を表わした一部拡大平面図、第６図はエツチ
ング工程の説明図である。 ２０……回路基板、２１……ＩＣ、Ｐｎ（Ｐ１
３〜Ｐ２５）……ＩＣ外部電極、Ｂｎ（Ｂ１３〜
Ｂ２５）……ボンデイングパターン、２５……狭
小部、２６……広幅部。
の一部の拡大平面図、第４図は従来例を模式的に
表わした従来例の一部平面図、第５図は従来例の
欠陥を表わした一部拡大平面図、第６図はエツチ
ング工程の説明図である。 ２０……回路基板、２１……ＩＣ、Ｐｎ（Ｐ１
３〜Ｐ２５）……ＩＣ外部電極、Ｂｎ（Ｂ１３〜
Ｂ２５）……ボンデイングパターン、２５……狭
小部、２６……広幅部。
Claims (1)
- 【実用新案登録請求の範囲】 (1) ＩＣチツプを搭載し、Ａｕ線等の導体材料
により電気的接続を行うことのできるボンデイン
グパターンを有する回路基板において、隣接する
ボンデイングパターンのボンデイング有効範囲周
辺が均一な隙間で構成されていることを特徴とす
る回路基板。 (2) 上記隙間が０．１２５mmで構成されている
ことを特徴とする請求項１記載の回路基板。 (3) 上記ボンデイング有効範囲が、ＩＣチツプ
のパツド中心から０．８〜１．５mmの範囲に配設
されていることを特徴とする請求項１記載の回路
基板。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990048734U JPH048432U (ja) | 1990-05-10 | 1990-05-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990048734U JPH048432U (ja) | 1990-05-10 | 1990-05-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH048432U true JPH048432U (ja) | 1992-01-27 |
Family
ID=31565816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990048734U Pending JPH048432U (ja) | 1990-05-10 | 1990-05-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH048432U (ja) |
-
1990
- 1990-05-10 JP JP1990048734U patent/JPH048432U/ja active Pending