JPH05335941A - Automatic phase controller - Google Patents

Abstract

PURPOSE:To reduce power consumption and to facilitate the design of share of delays. CONSTITUTION:Pulse signals S37, 38 whose polarity changes at a polarity change point of a data signal S31 and having a pulse width equivalent to a delay time of a fixed delay line 44 are generated based on the data signal S31 with an exclusive OR circuit 43 and the fixed delay line 44. Moreover, a pulse signal S39 whose polarity changes at a polarity change point of a pulse signal S38 and having a pulse width equivalent to a phase difference between the data signal S31 and a clock signal S35 is obtained based on the pulse signal S38 and the clock signal S35 with an exclusive OR circuit 46. Then, a phase control signal S33 is generated based on the pulse signals S37, S39. Thus, the phase of the clock signal is set to an object phase specified by a delay time of the fixed delay line 44.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic phase control device for automatically positioning the phase of a clock signal for identifying and reproducing a data signal at a target phase in a repeater of an optical transmission system.

[0002]

2. Description of the Related Art Generally, in an optical transmission system, a repeater is provided on an optical transmission line, and this repeater discriminates and reproduces a data signal to transmit the data signal to a destination.

The identification reproduction is usually performed by latching the equalized data signal with a predetermined clock signal.

In such a structure, the reproduction quality of the data signal is greatly influenced by the phase of the clock signal with respect to the data signal. Therefore, in order to improve the reproduction quality, it is necessary to position the phase of the clock signal at a predetermined target phase.

Conventionally, the repeater is provided with a delay line or a delay element for delaying the clock signal, and the delay time of the delay line or the delay element is adjusted at the time of shipping test of the repeater to adjust the phase of the clock signal. Was set to the target phase.

However, such a configuration has a problem that the work of adjusting the repeater at the time of shipping test becomes complicated and the number of adjustment steps increases.

Therefore, in recent years, the phase difference between the data signal and the clock signal is detected, and the phase of the clock signal is controlled based on the detected output to automatically position the phase of the clock signal to the target phase. Automatic phase control devices have been developed.

FIG. 2 is a block diagram showing a conventional structure of such an automatic phase control device. The device shown is Showa 6
3rd IEICE Spring National Convention, B-652 and B
-653.

Referring to FIG. 2, first, a schematic structure of this apparatus will be described.

In this apparatus, the clock signal S13 and the clock signal S14 for identification and reproduction have a phase difference φ1 so that the phase difference φ2 between the phase of the data signal S13 and the target phase of the clock signal S14 matches. The phase of this clock signal S14 is positioned at the target phase by controlling the phase of S14.

Here, the phase difference φ1 is determined by the data signal S13.
And the clock signal S14 are compared in phase. However, the phase comparison output changes according to the probability P that the polarity of the data signal S13 changes even if the phase difference φ1 does not change. So, in the device of FIG.
The signal S19 indicating the phase difference φ2 includes a component indicating the probability P, and this signal S19 and the signal S1 indicating the phase comparison result are included.
The phase control signal S12 is generated by subtracting 6 from the phase control signal S12.

According to this structure, the component indicating the probability P is canceled by the subtraction process, and the signal S12 indicating the difference between the phase difference φ1 and the phase difference φ2 is obtained. In other words, the signal S12 indicating the difference between the phase of the clock signal S14 and its target phase is obtained. Therefore, this signal S1
If the phase of the clock signal S14 is controlled by 2, the phase of the clock signal S14 can be positioned at the target phase.

In FIG. 2, the signal S16
Is obtained by taking the exclusive OR of the inputs and outputs of the latch circuit 16 for identification reproduction. Further, the signal 19 is the identification reproduction output as the clock signal S1.
4 using the clock signal S17 having a phase opposite to that of 4
It is obtained by latching at 0 and taking the exclusive OR of the input and output of this latch circuit 20.

In such a configuration, the phase difference φ
2 is set to the time width τ of the half cycle of the clock signal S14, in other words, the time width of 1/2 bit of the data signal S13. As a result, the phase of the clock signal S14 is positioned at the center of each bit of the data signal S13.

The above is the schematic configuration of the apparatus shown in FIG.
Next, a specific configuration of this device will be described.

In the figure, the clock signal S11 input from the clock input terminal 11 is supplied to the phase variable circuit 12. The phase of the clock signal S11 supplied to the phase variable circuit 12 is controlled based on the phase control signal S12. The phase control signal S12 is generated as follows.

That is, the data signal S13 input from the data input terminal 13 is branched into two by the buffer circuit 14. Of these two branch outputs, one is supplied to the exclusive OR circuit 15 and the other is supplied to the latch circuit 16 for identification reproduction.

The data signal S supplied to the latch circuit 16
13 is latched by the identification reproduction clock signal S14 output from the positive phase output terminal of the phase variable circuit 12. As a result, the identification reproduction output S15 of the input data signal S13 is obtained.

The identification reproduction output S15 is branched into two by the buffer circuit 17. Of the two branch outputs, one is supplied to the exclusive OR circuit 15 and the other is supplied to the buffer circuit 18.

The discrimination reproduction output S15 supplied to the exclusive OR circuit 15 is exclusive ORed with the data signal S13 supplied from the buffer circuit 14. As a result, at the output terminal of the exclusive OR circuit 15, the polarity changes at the polarity changing point of the data signal S13, and the pulse signal S16 having the pulse width corresponding to the phase difference φ1 is obtained.

The identification reproduction output S15 supplied to the buffer circuit 18 is branched into two. One of the two branch outputs is supplied to the exclusive OR circuit 19, and the other is supplied to the latch circuit 20.

The identification reproduction output S15 supplied to the latch circuit 20 is latched by the clock signal S17 output from the negative phase output terminal of the phase variable circuit 12. The latch output S18 is branched into two by the buffer circuit 21. Of these two branch outputs, one is supplied to the exclusive OR circuit 19, and the other is supplied to the data output terminal 22 as the final identification reproduction output of the data signal S13.

The latch output S18 supplied to the exclusive OR circuit 19 is exclusive ORed with the identification reproduction output S15 supplied from the buffer circuit 18. As a result, at the output terminal of the exclusive OR circuit 19, the polarity changes at the polarity changing point of the identification reproduction output S15, and the pulse signal S19 having the pulse width corresponding to the time width τ is obtained.

The pulse signals S16 and S19 are integrated by the integrating circuits 23 and 24, respectively, and then differentially amplified by the operational amplifier 25. As a result, the component indicating the probability P is canceled out, and a DC voltage corresponding to the difference between the phase difference φ1 and the time width τ is obtained.

This DC voltage is the phase control signal S12.
Is supplied to the phase variable circuit 12. As a result, the clock signal S is adjusted so that the phase difference φ1 matches the time width τ.
The 14 phases are controlled. As a result, the phase of this clock signal S14 is positioned at the center of each bit of the data signal S13.

FIG. 3 and FIG. 4 are waveform charts showing the signal waveforms of the respective parts of FIG.

As shown in FIG. 3, the pulse signal S16 output from the exclusive OR circuit 15 is the input data signal S1.
It becomes a high level at the polarity change point of 1 and becomes a pulse signal having a pulse width corresponding to the phase difference φ1. Also,
The pulse signal S19 output from the exclusive OR circuit 19
Becomes a high level at the change point of the identification reproduction output S15,
The pulse signal has a pulse width corresponding to the time width τ.

As a result, the integrated output S20 of the pulse signal S16 gradually increases as the phase difference φ1 increases, as shown in FIG. On the other hand, the integrated output S21 of the pulse signal S19 does not change even if the phase difference φ1 changes.
In this case, both integrated outputs S21 and S22 coincide when the phase difference φ1 is π, in other words, when the phase difference φ1 is τ. As a result, the phase of the clock signal S14 is controlled so as to converge to the center of the bits of the data signal S13.

[0029]

According to the conventional automatic phase control device described in detail above, the phase of the clock signal can be automatically positioned at the target phase, so that the repeater adjustment work during the shipping test is performed. Can be simplified and the number of adjustment steps can be reduced.

However, in the case of this device, in addition to the latch circuit 16 for identification reproduction, a reference signal (pulse signal S19)
A latch circuit 20 for generation is required, and moreover, a large number of buffer circuits 14, 17 for branching a high frequency signal,
Since 18 and 21 are also required, it is very difficult to design a delay distribution that takes into consideration the problem of increased power consumption, delay time variation of each gate element and delay time variation due to temperature / power supply variation. There was a problem.

Therefore, it is an object of the present invention to provide an automatic phase control device which reduces power consumption by reducing the number of gates and which allows easy design of delay distribution.

[0032]

In order to achieve the above object, the present invention comprises a first exclusive OR means for taking an exclusive OR of a data signal and a signal obtained by delaying the data signal by a predetermined time, Second exclusive OR means for taking an exclusive OR of the exclusive OR output of the first exclusive OR means and the clock signal output from the phase varying means, and the first and second exclusive OR Based on the exclusive OR output of the logical OR means,
A phase control signal generating means for generating a phase control signal is provided.

[0033]

In the above structure, the polarity is changed at the polarity change point of the data signal and the pulse signal having the pulse width corresponding to the delay time is obtained from the first exclusive OR means.

Further, the polarity of the second exclusive OR means changes at the polarity change point of the exclusive OR output of the first exclusive OR means, resulting in a phase difference between the data signal and the clock signal. A pulse signal with a corresponding pulse width is obtained.

Therefore, if the phase of the clock signal is controlled based on these two pulse signals, the phase of the clock signal can be positioned at the target phase defined by the delay time.

According to such a configuration, it is not necessary to use a latch circuit and the number of buffer circuits can be halved as compared with the conventional one, so that the power consumption is small and the delay distribution design is easy. An automatic phase control device can be realized.

[0037]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention.

In this embodiment, the phase difference φ1 as described above is used.
In the point of generating a signal including a component indicating the phase difference and a component indicating the probability P, a signal including a component indicating the phase difference φ2 and a component indicating the probability P, and generating a phase control signal based on both signals, The device is the same.

However, in this embodiment, the configuration for generating these two signals is different from the conventional device.

That is, in FIG. 1, the data signal S31 input to the data input terminal 31 is transferred to the buffer circuit 3
It is branched into two by 2. Of these two branch outputs, one is supplied to the latch circuit 33 which constitutes an identification reproduction circuit, and the other is supplied to the buffer circuit 42 of the automatic phase control device 40 described later.

The data signal S supplied to the latch circuit 33.
31 is latched by the clock signal S34 supplied from the phase variable circuit 41 of the automatic phase control device 40. The latch output is supplied to the data output terminal 34 as the identification reproduction output of the data signal.

Next, an automatic phase control device which is a feature of the present invention will be described. The clock signal S32 input from the clock input terminal 35 is supplied to the phase variable circuit 41 of the phase control device 40. The clock signal S32 supplied to the phase variable circuit 41 is the phase control signal S3 described later.
The phase is controlled based on 3. As a result, the clock signal positioned at the target phase is obtained.

In the figure, as such a clock signal,
For example, three clock signals S34, S35, S36 are shown. In this case, the clock signal S34 is as described above.
Used as a clock signal for identification reproduction. Further, the clock signal S35 is used as a clock signal for phase comparison. Further, the clock signal S36 is supplied to the clock output terminal 36, and is used for processing other than the identification / reproduction processing, for example.

In such a structure, the phase of the clock signal S35 is positioned at the target phase by the phase control action of the phase control device 40. Then, the other clock signals S34 and S36 are generated, for example, by phase-shifting the clock signal 35.

The phase control signal S33 is generated as follows. That is, the data signal S31 supplied from the buffer circuit 32 to the buffer circuit 42 is branched into two. Of these two branch outputs, one is supplied to the exclusive OR circuit 43, and the other is supplied to the exclusive OR circuit 43 via the fixed delay line 44.

The delay time of the fixed delay line 44 is set to a time width τ corresponding to a half cycle of the clock signal S32. As a result, the output terminal of the exclusive OR circuit 43 changes its polarity at the polarity change point of the data signal S31 and the pulse signals S37 and S38 having a pulse width corresponding to the time width τ are described later. Is obtained.

The pulse signal S37 output from the positive phase output terminal of the exclusive OR circuit 37 is integrated by the integrating circuit 45. As a result, at the output terminal of the integrating circuit 45, the probability P that the polarity of the data signal S32 changes and the DC voltage corresponding to the time width τ can be obtained.

On the other hand, the pulse signal S38 output from the negative phase output terminal of the exclusive OR circuit 37 is supplied to the exclusive OR circuit 46. In this exclusive OR circuit 46,
Further, the clock signal S35 output from the phase variable circuit 41 is supplied.

Accordingly, the pulse signal S3 is applied to the negative phase output terminal of the exclusive OR circuit 46, which will be described in detail later.
The polarity changes at the polarity changing point of 8, and a pulse signal S39 having a pulse width corresponding to the phase difference φ1 between the data signal S32 and the clock signal S35 is obtained.

The pulse signal S39 is integrated by the integrating circuit 47. As a result, the DC voltage corresponding to the probability P and the phase difference φ1 is obtained at the output terminal of the integrating circuit 47.

The integrated outputs S40 of the integration circuit products 45 and 47,
S41 is differentially amplified by the operational amplifier 48. As a result, the output terminal of the operational amplifier 48 has the above-mentioned time width τ.
A DC voltage corresponding to the difference between the phase difference φ1 and the phase difference φ1 is obtained.

This DC voltage is supplied to the phase variable circuit 41 as the phase control signal S33. As a result, the phase of the clock signal S35 output from the phase varying circuit 41 is positioned at the target phase defined by the time width τ.

FIGS. 5 and 6 are waveform charts showing signal waveforms of respective portions of FIG.

As shown in FIG. 5, the pulse signal S37 output from the positive phase output terminal of the exclusive OR 37 becomes high level at the polarity change point of the data signal S31 and has a pulse width corresponding to the time width τ. Become a signal. Similarly, the pulse signal S38 output from the negative-phase output terminal of the exclusive logic circuit 43 becomes a low level at the polarity change point of the data signal S31 and has a pulse width corresponding to the time width τ.

Further, as shown in FIG. 5, the pulse signal S39 output from the negative phase output terminal of the exclusive OR circuit 46 becomes high level at the polarity changing point of the pulse signal S38, and corresponds to the phase difference φ1. The signal has a pulse width.

As a result, the integration output S4 of the integration circuit 45 is obtained.
As shown in FIG. 6, 0 is a DC voltage that does not change even if the phase difference φ1 changes. On the other hand, the integrated output S of the integrating circuit 47
41 gradually increases based on the change of the phase difference φ1 when the phase difference φ1 is between 0 and π, and increases the phase difference φ1 when the phase difference φ1 is between π and 2π. Based on this, the DC voltage gradually decreases.

As a result, the clock signal S35 becomes π / 2 (τ /) from the rising edge of the data signal S31.
2) Positioned at a position deviated by only. In this case, if the shift amount of the clock signal S34 with respect to the clock signal S35 is set to π / 2, the phase of the clock signal S34 can be positioned at the center of each bit of the data signal S32.

As described above in detail, in this embodiment, the exclusive OR circuit 43 and the fixed delay line 44 allow the data signal S to be transmitted.
The pulse signals S37 and S38 indicating the polarity change point of 31 and the target phase of the clock signal S35 are generated, and the exclusive OR circuit 46 generates the pulse signal S39 indicating the polarity change point of the data signal S31 and the phase difference φ1. , Pulse signal S3
7 and S39, the phase of the clock signal S35 is controlled.

According to this structure, although the fixed delay line 44 is increased as compared with the conventional structure, the latch circuit can be eliminated and the number of buffer circuits can be halved, so that the power consumption is reduced. Moreover, it is possible to realize an automatic phase control device in which the design of delay distribution is easy.

FIG. 7 is a block diagram showing the configuration of the second embodiment of the present invention. 7, the same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the above embodiment, the case where the clock signal S32 is applied from the outside has been described. On the other hand, in this embodiment, the clock signal S32 is extracted from the data signal S31 by utilizing the configuration of the automatic phase control device 40.

That is, when the clock signal S32 is not given from the outside, it is necessary to extract the clock signal S32 from the data signal S31.

In this case, the data signal S31 is RZ (Re
If the signal has a clock component, such as a "turn to Zero" signal, the clock component can be extracted by directly passing the data signal S31 through a filter.

However, the data signal S31 is NRZ (No
In the case of a signal that does not have a clock component, such as an n Return to Zero signal, it is necessary to use a differentiating circuit to extract this clock component.

Therefore, in this embodiment, the phase controller 40 is used.
In consideration of the fact that the exclusive OR circuit 43 and the fixed delay line 44 of FIG. 6 differentiate the data signal S31 as a result, the differential component is used to extract the clock component.

That is, the pulse signal S37 output from the positive phase output terminal of the exclusive OR circuit 43 is supplied to the clock extraction circuit 50 composed of the bandpass filter 51 and the limiter amplifier 52.

As a result, the clock component is extracted from the pulse signal S37 which is the differential output of the data signal S31. This clock component is the clock signal S32.
It is supplied to the phase variable circuit 41 and used for phase control.

According to such a configuration, the pulse signal S3
Since the circuit for generating 7 can be shared with the differentiating circuit for extracting the clock component, it is possible to contribute to lower power consumption when extracting the clock component from the data signal having no clock component.

Even in the conventional device, the exclusive OR circuit 19 and the latch circuit 20 form a differentiating circuit.

However, in this case, since the latch circuit 20 is driven by the clock signal S17 corresponding to the input clock signal S11, this differentiating circuit cannot be used as a differentiating circuit for extracting the clock component.

On the other hand, in this embodiment, since the differentiating circuit is not composed of the latch circuit driven by the clock signal, this differentiating circuit can be used for extracting the clock component.

Although the two embodiments of the present invention have been described in detail above, the present invention is not limited to the above-mentioned embodiments.

For example, in the above embodiment, the case where the present invention is applied to the phase control of the clock signal for identification reproduction has been described. However, the present invention can also be applied to phase control of clock signals used for other processing.

In addition to the above, the present invention can of course be variously modified without departing from the scope of the invention.

[0075]

As described in detail above, according to the present invention,
It is possible to provide an automatic phase control device with low power consumption and easy design of delay distribution.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional automatic phase control device.

FIG. 3 is a signal waveform diagram for explaining the operation of FIG.

FIG. 4 is a signal waveform diagram for explaining the operation of FIG.

5 is a signal waveform diagram for explaining the operation of FIG. 1. FIG.

FIG. 6 is a signal waveform diagram for explaining the operation of FIG.

FIG. 7 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

[Explanation of symbols]

31 ... Data input terminal, 32, 42 ... Buffer circuit, 3
3 ... Latch circuit, 34 ... Data output terminal, 35 ... Clock input terminal, 36 ... Clock output terminal, 40 ... Automatic phase control device, 41 ... Phase variable circuit, 43, 46 ... Exclusive OR circuit, 44 ... Fixed delay Lines, 45, 47 ... Integrating circuit,
48 ... Operational amplifier, 50 ... Clock extraction circuit, 51 ... Band pass filter, 52 ... Limiter amplifier.

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H04L 7/033 (72) Inventor Shusei Aoki 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. Within

Claims (2)

[Claims] 1. An automatic phase control device for automatically positioning a phase of a clock signal for processing a data signal at a target phase, comprising: a phase control signal for positioning a phase of the clock signal at the target phase; Phase changing means for controlling the phase of the clock signal, delay means for delaying the data signal for a predetermined time, and first exclusive OR for taking exclusive OR of the delayed output of the delay means and the data signal. Means, second exclusive OR means for taking an exclusive OR of the exclusive OR output of the first exclusive OR means and the phase control output of the phase varying means, and the first and the first 2. An automatic phase control device comprising: a phase control signal generation means for generating the phase control signal based on the exclusive OR output of the exclusive OR means 2. 2. The automatic phase control according to claim 1, wherein the clock signal is configured to be generated based on an exclusive OR output of the first exclusive OR means. apparatus.