JPH0565896B2 - - Google Patents

Info

Publication number
JPH0565896B2
JPH0565896B2 JP59038566A JP3856684A JPH0565896B2 JP H0565896 B2 JPH0565896 B2 JP H0565896B2 JP 59038566 A JP59038566 A JP 59038566A JP 3856684 A JP3856684 A JP 3856684A JP H0565896 B2 JPH0565896 B2 JP H0565896B2
Authority
JP
Japan
Prior art keywords
data
dma transfer
dma
signal source
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59038566A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60183665A (ja
Inventor
Shinichi Iwaki
Tetsuo Takemura
Koichi Shimizu
Tatsuro Takahashi
Naoya Aragaki
Yasumasa Iwase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
NTT Inc
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP3856684A priority Critical patent/JPS60183665A/ja
Publication of JPS60183665A publication Critical patent/JPS60183665A/ja
Publication of JPH0565896B2 publication Critical patent/JPH0565896B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP3856684A 1984-03-02 1984-03-02 Ｄｍａ転送システム Granted JPS60183665A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3856684A JPS60183665A (ja) 1984-03-02 1984-03-02 Ｄｍａ転送システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3856684A JPS60183665A (ja) 1984-03-02 1984-03-02 Ｄｍａ転送システム

Publications (2)

Publication Number Publication Date
JPS60183665A JPS60183665A (ja) 1985-09-19
JPH0565896B2 true JPH0565896B2 (de) 1993-09-20

Family

ID=12528846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3856684A Granted JPS60183665A (ja) 1984-03-02 1984-03-02 Ｄｍａ転送システム

Country Status (1)

Country Link
JP (1) JPS60183665A (de)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5953565B2 (ja) * 1978-08-23 1984-12-26 株式会社日立製作所 ダイレクトメモリアクセス制御装置
JPS56108121A (en) * 1980-01-31 1981-08-27 Nec Corp Reporting system for end of dma data transfer
JPS57203124A (en) * 1981-06-10 1982-12-13 Fujitsu Ltd Selecting system for transfer bus

Also Published As

Publication number Publication date
JPS60183665A (ja) 1985-09-19

Similar Documents

Publication Publication Date Title
US5175732A (en) Method and apparatus for controlling data communication operations within stations of a local-area network
US20050149665A1 (en) Scratchpad memory
CN111221759B (zh) 一种基于dma的数据处理系统及方法
US5793994A (en) Synchronous event posting by a high throughput bus
US6061757A (en) Handling interrupts by returning and requeuing currently executing interrupts for later resubmission when the currently executing interrupts are of lower priority than newly generated pending interrupts
KR900016876A (ko) 공통 버스제어방법 및 시스템
JP2734246B2 (ja) パイプラインバス
JPS58105344A (ja) バツフアメモリ管理方式
US20050144338A1 (en) Data transfer apparatus
EP1139228A2 (de) Intelligente Busverbindungseinheit
US7620702B1 (en) Providing real-time control data for a network processor
US5875299A (en) disk access apparatus for performing a stride processing of data
JPS62182957A (ja) 通信トレ−ス方式
JPS60201453A (ja) 記憶装置アクセス制御方式
JP3458037B2 (ja) スプリットバス制御方式
JP2000244585A (ja) バスインタフェース回路
JP2789654B2 (ja) バッファ制御方式
JP2000003332A (ja) 双方向バスサイズ変換回路
JPH0567055A (ja) 外部バスを複数有するマルチプロセツサシステム
JPH0644258B2 (ja) Ｄｍａ転送先バッファ設定方式
JPH02310649A (ja) 受信フレーム転送方式および通信制御装置
JPH0439700B2 (de)
JPH02245858A (ja) データ転送制御装置
JP2000207350A (ja) デ―タ転送装置及びデ―タ転送方法
JPH07334453A (ja) メモリアクセスシステム