JPH0622263B2 - Method for manufacturing semiconductor substrate - Google Patents
Method for manufacturing semiconductor substrateInfo
- Publication number
- JPH0622263B2 JPH0622263B2 JP27015786A JP27015786A JPH0622263B2 JP H0622263 B2 JPH0622263 B2 JP H0622263B2 JP 27015786 A JP27015786 A JP 27015786A JP 27015786 A JP27015786 A JP 27015786A JP H0622263 B2 JPH0622263 B2 JP H0622263B2
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- JP
- Japan
- Prior art keywords
- semiconductor substrate
- type
- layer
- conductivity type
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体基板の製造方法に関し、特に選択エピタ
キシャル成長を用いた誘電体分離法をとる半導体基板の
製造方法に関する。TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to a method for manufacturing a semiconductor substrate using a dielectric isolation method using selective epitaxial growth.
従来、この種の半導体基板の製造方法では、第3図に示
すように絶縁用酸化膜303の下にP+形チャネルスト
ッパー302を形成するが、N+形埋込層306との接
合ができて容量が増加し周波数特性が悪化するのを防ぐ
ために、目合せズレおよび拡散横拡がり等を考慮したマ
ージン311をとっていた。Conventionally, in this type of semiconductor substrate manufacturing method, the P + type channel stopper 302 is formed under the insulating oxide film 303 as shown in FIG. 3, but it can be bonded to the N + type buried layer 306. In order to prevent the capacity from increasing and the frequency characteristics to deteriorate, the margin 311 is taken into consideration in consideration of misalignment and lateral spread of diffusion.
上述した従来の半導体基板の製造方法では、P+形チャ
ネルストッパーとN+形埋込層との接合により容量が増
加して周波数特性が悪化するのを防ぐために、目合せズ
レおよび拡散横拡がり等を考慮したマージンをとってい
るために、素子サイズが大きくなるという欠点がある。In the above-mentioned conventional method for manufacturing a semiconductor substrate, in order to prevent the capacitance from increasing and the frequency characteristics from deteriorating due to the junction between the P + type channel stopper and the N + type buried layer, misalignment, lateral spread, etc. Since the margin is taken into consideration, there is a drawback that the element size becomes large.
誘電体分離法の特徴は高集積化および容量低減による高
速化であるが、従来の方法を用いた場合、高集積化およ
び容量低減という点では大きな改善は望めなかった。The characteristics of the dielectric isolation method are high integration and high speed due to capacitance reduction. However, when the conventional method is used, no significant improvement can be expected in terms of high integration and capacitance reduction.
選択エピタキシャル成長を用いた誘電体分離法における
上述した従来のP+形チャネルストッパーとN+形埋込
層の形成方法に対し、本発明ではP+形チャネルストッ
パーとN+形埋込層をセルフアラインで形成するためP
+チャネルストッパーとN+形埋込層とのマージンをと
る必要がなく、素子サイズを縮小化でき、さらには接合
容量の低減による高速化もできるという利点がある。In contrast to the conventional method of forming a P + type channel stopper and an N + type buried layer in the dielectric isolation method using selective epitaxial growth, the present invention self-aligns the P + type channel stopper and the N + type buried layer. To form with P
There is an advantage that it is not necessary to take a margin between the + channel stopper and the N + type buried layer, the element size can be reduced, and further, the junction capacitance can be reduced to increase the speed.
本発明の半導体基板の製造方法は、第一導電形の半導体
基板の表面にこの半導体基板と同じ導電形で高濃度層を
形成しさらに絶縁物を形成する工程と、この絶縁物を半
導体素子を形成する領域のみ選択的に除去しさらに前記
領域の前記高濃度層を貫通して前記半導体基板の一部を
除去する工程と、前記絶縁物、前記高濃度層および前記
半導体基板の一部のそれぞれを除去した前記領域にのみ
選択的に前記第一導電形と反対導電形のエピタキシャル
層を形成する工程とを有している。A method of manufacturing a semiconductor substrate of the present invention comprises a step of forming a high-concentration layer on the surface of a semiconductor substrate of the first conductivity type with the same conductivity type as that of the semiconductor substrate and further forming an insulator, and forming the insulator into a semiconductor element. Selectively removing only a region to be formed and further removing a part of the semiconductor substrate by penetrating the high concentration layer in the region, and each of the insulator, the high concentration layer and a part of the semiconductor substrate. And selectively forming an epitaxial layer having a conductivity type opposite to that of the first conductivity type only in the region where is removed.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第1図(a),(b),(c)は本発明の実施例1の工
程を示す縦断面図である。1 (a), (b), and (c) are vertical cross-sectional views showing the steps of the first embodiment of the present invention.
101はP−形半導体基板で、この半導体基板上に絶縁
用酸化膜103を1〜2μm程度形成する。この時、P
−形半導体基板101と絶縁用酸化膜103との間にP
+形チャネルストッパー102を形成しておく(第1図
(a))。Reference numeral 101 is a P − type semiconductor substrate, and an insulating oxide film 103 is formed on this semiconductor substrate to a thickness of about 1 to 2 μm. At this time, P
P between the − type semiconductor substrate 101 and the insulating oxide film 103
A + type channel stopper 102 is formed (FIG. 1 (a)).
その後、フォトレジストをマスクとしてドライエッチン
グを行ない、選択的に絶縁用酸化膜103・P+形チャ
ネルストッパー102・P−形半導体基板101(の一
部)を除去してホール104を形成する(第1図
(b))。Then, dry etching is performed using the photoresist as a mask to selectively remove the insulating oxide film 103, P + -type channel stopper 102, and P − -type semiconductor substrate 101 (a part thereof) to form a hole 104 (first). Figure 1 (b)).
その後、ホール104にのみ選択的にN形エピタキシャ
ル層105を成長することにより半導体基板を形成する
(第1図(c))。After that, a semiconductor substrate is formed by selectively growing the N-type epitaxial layer 105 only in the holes 104 (FIG. 1 (c)).
第2図(a),(b),(c)は本発明の実施例2の工
程を示す縦断面図である。2 (a), (b), and (c) are vertical sectional views showing steps of the second embodiment of the present invention.
実施例1と同様な工程によりホール204を形成する
(第2図(a),(b))。The hole 204 is formed by the same process as that of the first embodiment (FIGS. 2A and 2B).
その後、ホール204に選択的にN形エピタキシャル成
長を行なうが、NPNトランジスタを構成した時のコレ
クタ抵抗を下げる目的で、N形エピタキシャル層205
と207との中間にN+形埋込層206を形成する(第
2図(c))。このN+形埋込層206の形成はN形エ
ピタキシャル層205を成長後N形不純物を高濃度に導
入することにより可能であり、また、N形エピタキシャ
ル層を形成中に不純物の導入量をコントロールすること
でも可能である。After that, N-type epitaxial growth is selectively performed in the holes 204, but the N-type epitaxial layer 205 is used for the purpose of lowering the collector resistance when the NPN transistor is formed.
And 207, an N + -type buried layer 206 is formed (FIG. 2 (c)). The N + -type buried layer 206 can be formed by growing the N-type epitaxial layer 205 and then introducing an N-type impurity at a high concentration, and the amount of the impurity introduced can be controlled during the formation of the N-type epitaxial layer. It is also possible to do
第4図は、実施例2を用いてNPNトランジスタを形成
した応用例の縦断面図である。第2図(c)におけるN
型エピタキシャル層207にP形ベース層408,N+
形コレクタ層410,N+形エミッタ層409を形成し
てNPNトランジスタを構成する。FIG. 4 is a vertical sectional view of an application example in which an NPN transistor is formed by using the second embodiment. N in FIG. 2 (c)
The P type base layer 408, N +
Forming a shaped collector layer 410, N + -type emitter layer 409 constituting the NPN transistor.
以上説明したように本発明は、第一導電形の高濃度のチ
ャネルストッパーを何ら制限なく形成することが可能で
あり、また、第一導電形と反対導電形の高濃度の埋込層
とのマージンもとる必要がないことから、素子の縮小化
および容量低減によるトランジスタの高速化ができる効
果がある。INDUSTRIAL APPLICABILITY As described above, according to the present invention, it is possible to form a high-concentration channel stopper of the first conductivity type without any limitation. Since it is not necessary to obtain a margin, there is an effect that the speed of the transistor can be increased by reducing the size of the element and reducing the capacity.
第1図は本発明の実施例1の工程を示す縦断面図、第2
図は本発明の実施例2の工程を示す縦断面図、第3図は
従来の半導体基板の製造方法による構造例の縦断面図、
第4図は本発明の一応用例の構造の縦断面図である。 101,201,301……P−形半導体基板、10
1,202,302……P+形チャネルストッパー、1
03,203,303……絶縁用酸化膜、104,20
4……ホール、105,205,207,307……N
形エピタキシャル層、206,306……N+形埋込
層、308,408……P形ベース層、309,409
……N+形エミッタ層、310,410……N+形コレ
クタ層。FIG. 1 is a longitudinal sectional view showing a process of Example 1 of the present invention,
FIG. 3 is a vertical cross-sectional view showing a process of Embodiment 2 of the present invention, FIG. 3 is a vertical cross-sectional view of a structural example by a conventional semiconductor substrate manufacturing method,
FIG. 4 is a vertical cross-sectional view of the structure of an application example of the present invention. 101,201,301 ...... P - type semiconductor substrate, 10
1,202,302 ... P + type channel stopper, 1
03, 203, 303 ... Insulating oxide film, 104, 20
4 ... Hall, 105,205,207,307 ... N
-Type epitaxial layer, 206, 306 ... N + -type buried layer, 308, 408 ... P-type base layer, 309, 409
... N + type emitter layer, 310, 410 ... N + type collector layer.
Claims (1)
体基板と同じ導電形で高濃度層を形成しさらに絶縁物を
形成する工程と、 この絶縁物を半導体素子を形成する領域のみ選択的に除
去しさらに前記領域の前記高濃度層を貫通して前記半導
体基板の一部を除去する工程と、 前記絶縁物、前記高濃度層および前記半導体基板の一部
のそれぞれを除去した前記領域にのみ選択的に前記第一
導電形と反対導電形のエピタキシャル層を形成する工程
とを有することを特徴とする半導体基板の製造方法。1. A step of forming a high-concentration layer on the surface of a semiconductor substrate of the first conductivity type with the same conductivity type as that of the semiconductor substrate and further forming an insulator, and selecting this insulator only in a region where a semiconductor element is formed. And further removing a part of the semiconductor substrate by penetrating the high concentration layer in the region, and the region in which the insulator, the high concentration layer and a part of the semiconductor substrate are removed, respectively. And a step of selectively forming an epitaxial layer having a conductivity type opposite to that of the first conductivity type, the method for manufacturing a semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27015786A JPH0622263B2 (en) | 1986-11-12 | 1986-11-12 | Method for manufacturing semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27015786A JPH0622263B2 (en) | 1986-11-12 | 1986-11-12 | Method for manufacturing semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63122238A JPS63122238A (en) | 1988-05-26 |
| JPH0622263B2 true JPH0622263B2 (en) | 1994-03-23 |
Family
ID=17482333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27015786A Expired - Lifetime JPH0622263B2 (en) | 1986-11-12 | 1986-11-12 | Method for manufacturing semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0622263B2 (en) |
-
1986
- 1986-11-12 JP JP27015786A patent/JPH0622263B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63122238A (en) | 1988-05-26 |
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