JPH0812867B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a semiconductor layer on a high resistance substrate as an operating layer.

[Prior art and its problems]

A semiconductor device using a semiconductor layer formed on a high-resistance substrate as an operating layer is easy to separate elements from each other, and a wiring connecting the elements to each other is formed on the high-resistance substrate so that parasitic capacitance is small. It has advantages and is suitable as an ultra-high speed digital integrated circuit. The most preferable example would be a gallium arsenide field effect transistor (hereinafter referred to as GaAs FET). Figure 1 shows the most basic cross-sectional shape of a GaAs FET.
In the figure, 11 is a semi-insulating GaAs substrate with a specific resistance of 10 ⁷ Ωcm, 1
2 is an ion implantation method (implantation energy 70 KeV. Implantation ion: Si
⁺ , The thickness formed by the dose amount 2 × 10 ¹² cm ^-2 ): About 1000
Å, n-type GaAs layer with carrier density n: 2 × 10 ¹⁷ cm ^-3 , 13 is a gate electrode made of, for example, Al, 14 and 15 are formed by vapor deposition of AuGe and then heat alloying at 400 ° C for 1 minute. Electrodes (14: source, 15: drain) that make ohmic contact. As with all semiconductor devices, GaAs FETs also have series parasitic resistance (source resistance R _{S in} this case).
Is required to improve device characteristics. This is because the transconductance gm of the FET is the value g when R _S = 0.
It is also clear from the fact that it becomes 1 / (1 + gm ₀ R _S ) of m ₀ , that is, the following equation holds.

Thus, although the reduction of R _S is indispensable for the improvement of gm, that is, the improvement of FET characteristics, conventionally, as a countermeasure against it, the distance between the source and the gate is shortened and the contact specific resistance ρ _C is reduced. However, no attention was paid to the optimization of the depth of the alloyed layer (alloy layer) for ohmic contact.

[Object of the Invention]

The present invention has been made in view of the above-mentioned drawbacks of the conventional semiconductor device, and an object thereof is to provide a semiconductor device having a small parasitic resistance of ohmic contact portion.

[Structure of Invention]

The present invention relates to a semiconductor device provided with an electrode which makes at least ohmic contact with a semiconductor operating layer on a high resistance substrate, particularly an ohmic electrode having an alloy layer formed by heat alloying an electrode metal and a semiconductor. The semiconductor device is characterized in that the thickness of the semiconductor layer is set to 2000 Å or less and 250 Å or more of the semiconductor layer is left between the alloy layer and the high resistance substrate.

[Principle and Action of the Present Invention]

Next, the principle of the present invention will be briefly described. Generally, an ohmic contact with a semiconductor crystal is formed by a heat alloying reaction between a metal containing impurities as a dopant and a semiconductor. For example, in the case of the GaAs FET shown in FIG.
It is formed by forming an Au film containing Ge on the crystal surface and then performing a heat treatment (alloy) at about 400 ° C. On this occasion
A large amount of Ge, which is an n-type dopant, was included in the GaAs crystal.
The N ⁺ layer (alloy layer) is formed to a certain depth. The depth of such an alloy layer is negligible compared to the thickness of the operating layer (semiconductor layer) in the case of a conventional element, for example, a GaAs FET for microwaves, but the ultra-high-speed digital signal described at the beginning In a GaAs FET used in an integrated circuit, the operating layer is thin (for example, 1000 Å in the case of FIG. 1), so the depth of the alloy layer cannot be ignored with respect to the operating layer thickness. The inventor calculated how much the depth (thickness) of this alloy layer should be set by using the model of FIG. In the figure, 20 is a semiconductor layer, 21 is an ohmic metal (for example, Au, Ge, N
i) and 22 are alloy layers (N ⁺ layers). The parasitic resistance R _S is composed of a resistance R _{1 in a} portion that vertically enters the alloy layer 22 from the lateral direction and a resistance R ₂ in a portion that wraps around the alloy layer 22 from below, and they are each calculated by the following equation.

Where w is the electrode width, n and μ are carrier densities of the semiconductor layer,
The electron mobility. The equation (4) is obtained using a normal transmission line model. An example of the calculation result is shown in FIG. Fig. 3 shows the relationship between t ₁ and R _S for a = 500Å, 1000Å, 2000Å (ρ _c = 10 ^-6 Ωc
m ² ), and the shaded area in the figure is the area at −t ₁ 2250Å, that is, the thickness t _{2 of the} semiconductor layer 20 remaining below the alloy layer 22
Shows an area of 250 Å or more. From the figure, it is understood that t ₂ should be 250 Å or more in order to make R _S sufficiently small, which is the background of the present invention. In the present invention (also in FIG. 3), a is only considered up to 2000Å, but when a> 2000Å, even if t ₂ 250Å, R _S
Is sufficiently small, and the parasitic resistance can be reduced without applying the present invention. In Fig. 3, ρ _c is 10 ^-6 Ω ・
cm ² and the specific resistance of the semiconductor layer is 1 / (e · n ·
μ) is 0.01 Ω · cm, but ρ _c is this value (10 ^-6
It is necessary and resistivity in Ω · cm ²⁾ or more is similar to t ₂ ≧ 250 Å in the case of less than 0.01 Ohm · cm.

〔Example〕

Next, an embodiment of the semiconductor device according to the present invention will be described taking the case of a GaAs FET as an example. FIG. 4 is a diagram for explaining the embodiment of the present invention, and 11 to 15 are the same as the components shown in FIG. The same numbers are assigned and the description is omitted. 41
Indicates the alloy layer conceptually. In this GaAs FET, since the operating layer thickness a is 1000Å, the thickness of the alloy layer 41 is
t ₁ is set to 750Å or less. Setting the thickness of the alloy layer 41 is intended primarily dependent on the thickness and alloy method AuGe depositing (alloy time) t ₁ in order to 500Å is A
It is appropriate to use 1200 Å for uGe, alloy time: 1 minute (alloy temperature 420 ° C), and to make it thinner, for example, 300 Å, AuGe thickness is 600 Å, and short-time annealing (flash annealing) etc. is applied as an alloy method. It is effective.

〔The invention's effect〕

As described above, by comparing the thickness of the alloy layer and leaving a semiconductor layer of 250 Å or more between the alloy layer and the high-resistance substrate, the alloy layer is set to penetrate the semiconductor layer as in the conventional case. _S is reduced to about 1/2, and gm can be improved by about 30%.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a conventional semiconductor device, and FIG.
FIG. 3 is a diagram showing the principle of a semiconductor device according to the present invention, FIG. 3 is a diagram showing the relationship between the thickness of a semiconductor layer and parasitic resistance, and FIG. 4 is a sectional view schematically showing an embodiment of the present invention. 11 ... Semi-insulating GaAs substrate, 12 ... N-type GaAs semiconductor layer, 13
...... Gate electrode, 14 ...... Source electrode, 15 …… Drain electrode, 21 …… Ohm electrode, 22 …… Alloy layer (N ⁺ layer), 41 ・ ・ ・
... alloy layer.

Claims (1)

[Claims] 1. A semiconductor operating layer on a high resistance semiconductor substrate,
A semiconductor provided with an ohmic electrode which is in ohmic contact with the semiconductor layer and which has an alloy layer formed by thermal alloying of a metal electrode containing a dopant impurity with the semiconductor layer and the semiconductor layer. A contact resistance of the ohmic electrode to the semiconductor layer is 1 × 10 ⁻⁶ Ω · cm ² or more, and the semiconductor layer has a specific resistance of 0.01 Ω · cm or less; Is set to 2000 angstroms or less, and a semiconductor layer of 250 angstroms or more is left between the alloy layer and the high resistance semiconductor substrate.