JPH09501802A - 高速電子回路用の誘電率の小さい材料の処理 - Google Patents
高速電子回路用の誘電率の小さい材料の処理Info
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Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.基板の上に誘電率の小さい材料を設ける方法において、誘電率の小さい層 に添加材料を分散させる工程と、前記層を基板の面に付着させる工程と、前記層 から添加材料を取り除く工程とを含むことを特徴とする方法。 2.前記層から添加材料を取り除く工程が、昇華、蒸発及び拡散からなる群か ら選ばれた方法で構成されている請求項1記載の方法。 3.前記添加材料が前記層中から昇華可能である請求項2記載の方法。 4.前記層が重合体及びセラミックからなる群から選ばれた材料で構成されて いる請求項2記載の方法。 5.前記層が気孔を持つ多孔質層で構成されている請求項4記載の方法。 6.前記基板が接続面にチップ・パッドを持つ回路チップを支持しており、前 記層を前記基板の面に付着させる工程が、前記層を前記回路チップの接続面に付 着させることを含み、更に、前記層から添加材料を取り除く前に、少なくとも1 つの前記チップ・パッドまで伸びる少なくとも1つのバイアを前記層中に形成し 、次いで前記層の上に導電材料のパターンを形成して、前記導電材料のパターン が前記少なくとも1つのバイアの中に入り込むようにする工程を含んでいる請求 項2記載の方法。 7.前記層が重合体層で構成されている請求項6記載の方法。 8.前記重合体層が気孔を持つ多孔質層で構成されている請求項7記載の方法 。 9.前記多孔質層がポリテトラフルオロエチレン、ポリエチレン及びポリスチ レンからなる群から選ばれた材料で構成されている請求項8記載の方法。 10.前記添加材料が、ろう、アントラキノン及び昇華可能な有機物からなる 群から選ばれた材料で構成されている請求項9記載の方法。 11.前記多孔質層を基板の面に付着させる工程が、前記多孔質層と前記基板 の面との間に接着剤を用いることを含む請求項8記載の方法。 12.前記接着剤がポリテトラフルオロエチレン及び酸化ポリフェニレンから なる群から選ばれた接着剤で構成されている請求項11記載の方法。 13.更に、前記導電材料のパターンを形成した後に、添加材料を分散させた 別の多孔質層を、接着剤を用いて前記多孔質層及び導電材料のパターンの面に付 着させ、次いで前記別の多孔質層中に、前記導電材料のパターンの一部分まで達 する別のバイアを形成し、次いで前記別の多孔質層の上に導電材料の別のパター ンを形成して、該導電材料の別のパターンが前記別のバイアに入り込みむように し、その後に前記別の多孔質層から添加材料を取り除く工程を含んでいる請求項 8記載の方法。 14.前記多孔質層から添加材料を取り除く工程及び前記別の多孔質層から添 加材料を取り除く工程が同時に行わ れる請求項13記載の方法。 15.前記多孔質層及び前記別の多孔質層が、第1のポリテトラフルオロエチ レン材料で構成され、前記接着剤が前記第1のポリテトラフルオロエチレン材料 よりも融点の低い第2のポリテトラフルオロエチレン材料で構成されている請求 項13記載の方法。 16.基板の上に誘電率の小さい材料を設けて削摩する方法において、誘電率 の小さい多孔質重合体層を基板の面に付着させる工程と、前記重合体層の上にマ スク材料を設ける工程と、該マスク材料の中に前記重合体層まで達するバイアを 形成する工程と、前記重合体層中の所定の領域に前記マスク材料中のバイアを介 して添加材料を拡散させる工程と、前記マスク材料を取り除き、前記添加材料を 拡散させ領域の所で、重合体材料の少なくとも若干を削摩する工程とを含むこと を特徴とする方法。 17.更に、残っている添加材料があれば、それを前記重合体層から昇華によ って取り除く工程を含む請求項16記載の方法。 18.前記重合体層がポリテトラフルオロエチレンで構成され、前記マスク材 料がポリイミドで構成されている請求項17記載の方法。 19.誘電率の小さい印刷配線板を作る方法において、誘電率の小さい層内に 添加材料を分散させる工程と、前記誘電率の小さい層の少なくとも1つの面の上 に接着剤を適用する工程と、該接着剤の上にメタライズ層を形成する工 程と、前記誘電率の小さい層、接着剤及びメタライズ層を通る複数個の孔を設け る工程と、前記メタライズ層をパターン成形する工程と、前記誘電率の小さい層 から前記添加材料を取り除く工程とを含むことを特徴とする方法。 20.前記誘電率の小さい層から添加材料を取り除く工程が、昇華、蒸発及び 拡散からなる群から選ばれた方法で構成される請求項19記載の方法。 21.前記添加材料が前記誘電率の小さい層の中を昇華可能である請求項20 記載の方法。 22.前記誘電率の小さい層が重合体層で構成されている請求項20記載の方 法。 23.前記重合体層が気孔を持つ多孔質層で構成されている請求項22記載の 方法。 24.前記多孔質層が、ポリテトラフルオロエチレン、ポリエチレン及びポリ スチレンからなる群から選ばれた材料で構成されている請求項23記載の方法。 25.前記添加材料が、ろう、アントラキノン及び昇華可能な有機物からなる 群から選ばれた材料で構成されている請求項24記載の方法。 26.基板と、チップ・パッドを持っていて、前記基板によって支持された回 路チップと、前記基板及び回路チップの上に設けられていて、少なくとも1つの チップ・パッドと整合した少なくとも1つのバイアを持つ誘電率の小さい多孔質 層と、前記多孔質層の一部分の上に伸びていて、前記少なくとも1つのバイアに 入り込む電気導体のパター ンとを有する構造。 27.前記多孔質層が重合体層で構成されている請求項26記載の構造。 28.前記重合体層がポリテトラフルオロエチレン、ポリエチレン及びポリス チレンからなる群から選ばれた材料で構成されている請求項27記載の構造。 29.更に、前記多孔質層と前記基板の面との間に接着剤を含んでいる請求項 26記載の構造。 30.前記接着剤が、ポリテトラフルオロエチレン及び酸化ポリフェニレンか らなる群から選ばれた接着剤で構成されている請求項29記載の構造。 31.更に、前記多孔質層の面及び前記電気導体のパターンの上にある別の多 孔質層と、前記多孔質層と前記別の多孔質層との間に配置された接着剤とを有し 、該別の多孔質層は前記電気導体のパターンの少なくとも一部分まで通抜ける別 のバイアを持っており、更に、前記別の多孔質層の上にある導電材料の別のパタ ーンを有し、該導電材料の別のパターンが前記別のバイアに入り込んでいる請求 項26記載の構造。 32.前記多孔質層及び前記別の多孔質層が第1のポリテトラフルオロエチレ ン材料で構成され、前記接着剤が前記第1のポリテトラフルオロエチレン材料よ りも融点の低い第2のポリテトラフルオロエチレン材料で構成されている請求項 31記載の構造。 33.誘電率の小さい層と、該誘電率の小さい層の少な くとも1つの面に重なる接着剤と、該接着剤の上に設けられたパターン成形した メタライズ層と、前記誘電率の小さい層、接着剤及びメタライズ層を通抜ける複 数個の孔とを有することを特徴とする、誘電率の小さい印刷配線板。 34.前記誘電率の小さい層が多孔質材料で構成されている請求項33記載の 誘電率の小さい印刷配線板。 35.前記誘電率の小さい層が重合体層で構成されている請求項34記載の誘 電率の小さい印刷配線板。 36.前記重合体層がポリテトラフルオロエチレン、ポリエチレン及びポリス チレンからなる群から選ばれた材料で構成されている請求項35記載の誘電率の 小さい印刷配線板。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/247,820 | 1994-05-23 | ||
| US08/247,820 US5449427A (en) | 1994-05-23 | 1994-05-23 | Processing low dielectric constant materials for high speed electronics |
| PCT/US1995/005983 WO1995032604A1 (en) | 1994-05-23 | 1995-05-15 | Processing low dielectric constant materials for high speed electronics |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
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| JP3769297B2 JP3769297B2 (ja) | 2006-04-19 |
Family
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| JP2005291845A Pending JP2006080544A (ja) | 1994-05-23 | 2005-10-05 | 高速電子回路用の誘電率の小さい材料の処理 |
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| EP (2) | EP0710430B1 (ja) |
| JP (2) | JP3769297B2 (ja) |
| CA (1) | CA2163627A1 (ja) |
| DE (2) | DE69533789T2 (ja) |
| WO (1) | WO1995032604A1 (ja) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2006022083A1 (ja) * | 2004-08-23 | 2006-03-02 | Sumitomo Electric Industries, Ltd. | 穿孔された多孔質樹脂基材及び穿孔の内壁面を導電化した多孔質樹脂基材の製造方法 |
| JP2010182723A (ja) * | 2009-02-03 | 2010-08-19 | Fujitsu Ltd | 半導体装置の製造方法 |
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- 1995-03-27 US US08/411,176 patent/US5576517A/en not_active Expired - Lifetime
- 1995-05-15 EP EP95920427A patent/EP0710430B1/en not_active Expired - Lifetime
- 1995-05-15 CA CA002163627A patent/CA2163627A1/en not_active Abandoned
- 1995-05-15 WO PCT/US1995/005983 patent/WO1995032604A1/en not_active Ceased
- 1995-05-15 JP JP53034195A patent/JP3769297B2/ja not_active Expired - Fee Related
- 1995-05-15 EP EP04020818A patent/EP1484949B1/en not_active Expired - Lifetime
- 1995-05-15 DE DE69533789T patent/DE69533789T2/de not_active Expired - Fee Related
- 1995-05-15 DE DE69535951T patent/DE69535951D1/de not_active Expired - Fee Related
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2005
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006022083A1 (ja) * | 2004-08-23 | 2006-03-02 | Sumitomo Electric Industries, Ltd. | 穿孔された多孔質樹脂基材及び穿孔の内壁面を導電化した多孔質樹脂基材の製造方法 |
| US7807066B2 (en) | 2004-08-23 | 2010-10-05 | Sumitomo Electric Industries, Ltd. | Method of manufacturing a porous resin substrate having perforations and method of making a porous resin substrate including perforations having electrically conductive wall faces |
| JP2010182723A (ja) * | 2009-02-03 | 2010-08-19 | Fujitsu Ltd | 半導体装置の製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1484949B1 (en) | 2009-05-06 |
| US5576517A (en) | 1996-11-19 |
| DE69535951D1 (de) | 2009-06-18 |
| CA2163627A1 (en) | 1995-11-30 |
| DE69533789D1 (de) | 2004-12-30 |
| EP0710430B1 (en) | 2004-11-24 |
| EP0710430A1 (en) | 1996-05-08 |
| JP2006080544A (ja) | 2006-03-23 |
| US5554305A (en) | 1996-09-10 |
| EP1484949A3 (en) | 2004-12-15 |
| US5449427A (en) | 1995-09-12 |
| JP3769297B2 (ja) | 2006-04-19 |
| DE69533789T2 (de) | 2005-11-24 |
| EP1484949A2 (en) | 2004-12-08 |
| WO1995032604A1 (en) | 1995-11-30 |
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