JPH11214662A5 - - Google Patents

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Publication number
JPH11214662A5
JPH11214662A5 JP1998017014A JP1701498A JPH11214662A5 JP H11214662 A5 JPH11214662 A5 JP H11214662A5 JP 1998017014 A JP1998017014 A JP 1998017014A JP 1701498 A JP1701498 A JP 1701498A JP H11214662 A5 JPH11214662 A5 JP H11214662A5
Authority
JP
Japan
Prior art keywords
region
transistors
gate
gate contact
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1998017014A
Other languages
English (en)
Other versions
JPH11214662A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP10017014A priority Critical patent/JPH11214662A/ja
Priority claimed from JP10017014A external-priority patent/JPH11214662A/ja
Priority to TW087110766A priority patent/TW393764B/zh
Priority to US09/126,092 priority patent/US6084255A/en
Priority to KR1019980034835A priority patent/KR19990066747A/ko
Publication of JPH11214662A publication Critical patent/JPH11214662A/ja
Publication of JPH11214662A5 publication Critical patent/JPH11214662A5/ja
Pending legal-status Critical Current

Links

Description

ＳＯＩ層１７には、その主面に沿って、ＰＭＯＳ領域ＲＰとＮＭＯＳ領域ＲＮとが形成されている。これらの領域は、対称軸ＳＡを境界として、その両側に対称に形成される。ＰＭＯＳ領域ＲＰは、ＰＭＯＳトランジスタが形成される領域であり、ＮＭＯＳ領域ＲＮは、ＮＭＯＳトランジスタが形成される領域である。すなわち、この装置１０１は、ＣＭＯＳトランジスタを回路要素とする回路の形成に適した装置として構成されている。
また、ゲート絶縁膜１３に対応してゲート絶縁膜１４、ゲート電極３に対応してゲート電極４、ゲートコンタクト領域５，６に対応して、ゲートコンタクト領域７，８が形成されている。ゲートコンタクト領域９およびゲートコンタクト領域１０は、それぞれボディ領域１１およびボディ領域１２の対称軸ＳＡから遠い方の一端に連結している。
さらに、図４に示すように、ゲートコンタクト領域７（または５）どうし、および、ボディコンタクト領域１０（または９）どうしは、分離絶縁膜２３によって電気的に絶縁されている。図示を略するが、ゲートコンタクト領域８（または６）どうしも、分離絶縁膜２３によって電気的に絶縁されている。これらの、分離絶縁膜２２〜２４は、いずれも、その上部は、ＳＯＩ層１７の上主面の上に露出するとともに、その底部は、絶縁層２１の上主面に達している。これによって、分離絶縁膜２２〜２４は、それらの両側に分け隔てられたＳＯＩ層１７の部分を互いに電気的に絶縁する。
さらに、トランジスタＱ１，Ｑ２に隣接するＭＯＳトランジスタ、すなわち、これらのトランジスタを挟むトランジスタについては、ゲートコンタクト領域５およびボディコンタクト領域９は、ともに、コンタクトホールＣＨおよび配線パターンＭ１を通じて電源配線３１へと接続されている。同様に、トランジスタＱ３，Ｑ４に隣接するＭＯＳトランジスタ、すなわち、これらのトランジスタを挟むトランジスタについては、ゲートコンタクト領域７およびボディコンタクト領域１０は、ともに、コンタクトホールＣＨおよび配線パターンＭ１を通じて電源配線３２へと接続されている。

JP10017014A 1998-01-29 1998-01-29 半導体装置 Pending JPH11214662A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP10017014A JPH11214662A (ja) 1998-01-29 1998-01-29 半導体装置
TW087110766A TW393764B (en) 1998-01-29 1998-07-03 Semiconductor device
US09/126,092 US6084255A (en) 1998-01-29 1998-07-30 Gate array semiconductor device
KR1019980034835A KR19990066747A (ko) 1998-01-29 1998-08-27 반도체 장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10017014A JPH11214662A (ja) 1998-01-29 1998-01-29 半導体装置

Publications (2)

Publication Number Publication Date
JPH11214662A JPH11214662A (ja) 1999-08-06
JPH11214662A5 true JPH11214662A5 (ja) 2005-08-11

Family

ID=11932156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10017014A Pending JPH11214662A (ja) 1998-01-29 1998-01-29 半導体装置

Country Status (4)

Country Link
US (1) US6084255A (ja)
JP (1) JPH11214662A (ja)
KR (1) KR19990066747A (ja)
TW (1) TW393764B (ja)

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US6677645B2 (en) 2002-01-31 2004-01-13 International Business Machines Corporation Body contact MOSFET
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US7910993B2 (en) 2005-07-11 2011-03-22 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink
US7890891B2 (en) 2005-07-11 2011-02-15 Peregrine Semiconductor Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US8742502B2 (en) 2005-07-11 2014-06-03 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US9653601B2 (en) 2005-07-11 2017-05-16 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US20080076371A1 (en) 2005-07-11 2008-03-27 Alexander Dribinsky Circuit and method for controlling charge injection in radio frequency switches
USRE48965E1 (en) 2005-07-11 2022-03-08 Psemi Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
JP4845177B2 (ja) * 2005-07-15 2011-12-28 ラピスセミコンダクタ株式会社 半導体装置
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7917879B2 (en) 2007-08-02 2011-03-29 Tela Innovations, Inc. Semiconductor device with dynamic array section
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
JP5041760B2 (ja) * 2006-08-08 2012-10-03 ルネサスエレクトロニクス株式会社 半導体集積回路装置
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US9948281B2 (en) 2016-09-02 2018-04-17 Peregrine Semiconductor Corporation Positive logic digitally tunable capacitor
JP6955566B2 (ja) * 2017-08-07 2021-10-27 タワー パートナーズ セミコンダクター株式会社 半導体装置
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JPH07283377A (ja) * 1994-01-03 1995-10-27 Texas Instr Inc <Ti> 小型ゲートアレイおよびその製造方法
JPH0951083A (ja) * 1995-08-10 1997-02-18 Mitsubishi Electric Corp ゲートアレイ型半導体集積回路装置及びその製造方法
JP2798056B2 (ja) * 1996-05-30 1998-09-17 日本電気株式会社 マスタスライス半導体集積回路

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