JPS51139274A - Method of manufacturing semi_conductor device - Google Patents
Method of manufacturing semi_conductor deviceInfo
- Publication number
- JPS51139274A JPS51139274A JP50062861A JP6286175A JPS51139274A JP S51139274 A JPS51139274 A JP S51139274A JP 50062861 A JP50062861 A JP 50062861A JP 6286175 A JP6286175 A JP 6286175A JP S51139274 A JPS51139274 A JP S51139274A
- Authority
- JP
- Japan
- Prior art keywords
- conductor device
- manufacturing semi
- cmosic
- semi
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Drying Of Semiconductors (AREA)
Abstract
PURPOSE:To manufacture a CMOSIC with high precision and with flat surface for preventing breakage of the A1 wiring by making use of a selectively plasma-etched silicon nitride film as diffusion mask for forming the source and drain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50062861A JPS51139274A (en) | 1975-05-28 | 1975-05-28 | Method of manufacturing semi_conductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50062861A JPS51139274A (en) | 1975-05-28 | 1975-05-28 | Method of manufacturing semi_conductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS51139274A true JPS51139274A (en) | 1976-12-01 |
Family
ID=13212489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50062861A Pending JPS51139274A (en) | 1975-05-28 | 1975-05-28 | Method of manufacturing semi_conductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS51139274A (en) |
-
1975
- 1975-05-28 JP JP50062861A patent/JPS51139274A/en active Pending
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