JPS5245885A - Semiconductor integrated circuit device and process for production of same - Google Patents
Semiconductor integrated circuit device and process for production of sameInfo
- Publication number
- JPS5245885A JPS5245885A JP50120731A JP12073175A JPS5245885A JP S5245885 A JPS5245885 A JP S5245885A JP 50120731 A JP50120731 A JP 50120731A JP 12073175 A JP12073175 A JP 12073175A JP S5245885 A JPS5245885 A JP S5245885A
- Authority
- JP
- Japan
- Prior art keywords
- production
- same
- integrated circuit
- semiconductor integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 230000010354 integration Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/65—Integrated injection logic
- H10D84/655—Integrated injection logic using field effect injector structures
Landscapes
- Logic Circuits (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To provide a gate electrode that should form an inversion layer on the surface of the base region of a lateral transistor, on said base region by way of an insulating film, thereby reducing an occupying area and increasing the scale of integration of an IIL ligic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50120731A JPS5245885A (en) | 1975-10-08 | 1975-10-08 | Semiconductor integrated circuit device and process for production of same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50120731A JPS5245885A (en) | 1975-10-08 | 1975-10-08 | Semiconductor integrated circuit device and process for production of same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5245885A true JPS5245885A (en) | 1977-04-11 |
Family
ID=14793581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50120731A Pending JPS5245885A (en) | 1975-10-08 | 1975-10-08 | Semiconductor integrated circuit device and process for production of same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5245885A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55159900U (en) * | 1979-05-01 | 1980-11-17 | ||
| US4395723A (en) * | 1980-05-27 | 1983-07-26 | Eliyahou Harari | Floating substrate dynamic RAM cell with lower punch-through means |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51117585A (en) * | 1975-04-09 | 1976-10-15 | Fujitsu Ltd | Semiconductor equipment |
| JPS5210088A (en) * | 1975-07-15 | 1977-01-26 | Nec Corp | Structure of semiconductor integrated circuit |
-
1975
- 1975-10-08 JP JP50120731A patent/JPS5245885A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51117585A (en) * | 1975-04-09 | 1976-10-15 | Fujitsu Ltd | Semiconductor equipment |
| JPS5210088A (en) * | 1975-07-15 | 1977-01-26 | Nec Corp | Structure of semiconductor integrated circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55159900U (en) * | 1979-05-01 | 1980-11-17 | ||
| US4395723A (en) * | 1980-05-27 | 1983-07-26 | Eliyahou Harari | Floating substrate dynamic RAM cell with lower punch-through means |
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