JPS5496367A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5496367A
JPS5496367A JP271778A JP271778A JPS5496367A JP S5496367 A JPS5496367 A JP S5496367A JP 271778 A JP271778 A JP 271778A JP 271778 A JP271778 A JP 271778A JP S5496367 A JPS5496367 A JP S5496367A
Authority
JP
Japan
Prior art keywords
layer
iron
lead frame
formation
formation process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP271778A
Other languages
Japanese (ja)
Inventor
Takashi Uchida
Takeyumi Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP271778A priority Critical patent/JPS5496367A/en
Publication of JPS5496367A publication Critical patent/JPS5496367A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To realize the cost reduction for the semiconductor device by forming the lead frame with iron or the iron alloy and providing the formation layer at least on part of the surface layer. CONSTITUTION:Lead frame 1 is formed by giving the press molding to the streak or plate substance 1' made of iron or the iron alloy, and precious metal coated layer 4 of gold or silver is formed at the edge of the lead and element installing table 1a. Then formation process layer 5 of the zinc phosphate film or the like is formed at the exposed part of iron (alloy) excluding layer 4. The connection is easy between layer 4 and electrode 6a of element 2 or metal thin wire 3b, 3c and others. After formation of resin sealing substance 7, the exposed area of the formation process film is removed with concentrated hydrochloric acid or the like, and then the solder layer or the like is coated. As the low-cost iron material is used for the lead frame, the production cost can be reduced down. At the same time, the formation process film functions to prevent the oxidation and the rust occurrence during the assembling processes.
JP271778A 1978-01-17 1978-01-17 Semiconductor device Pending JPS5496367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP271778A JPS5496367A (en) 1978-01-17 1978-01-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP271778A JPS5496367A (en) 1978-01-17 1978-01-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5496367A true JPS5496367A (en) 1979-07-30

Family

ID=11537051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP271778A Pending JPS5496367A (en) 1978-01-17 1978-01-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5496367A (en)

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