JPS55123715A - Initializing system - Google Patents
Initializing systemInfo
- Publication number
- JPS55123715A JPS55123715A JP3077979A JP3077979A JPS55123715A JP S55123715 A JPS55123715 A JP S55123715A JP 3077979 A JP3077979 A JP 3077979A JP 3077979 A JP3077979 A JP 3077979A JP S55123715 A JPS55123715 A JP S55123715A
- Authority
- JP
- Japan
- Prior art keywords
- unit
- fdc107
- rom103
- initialize
- hang
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000452 restraining effect Effects 0.000 abstract 1
Landscapes
- Retry When Errors Occur (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE: To initialize a unit with restraining the damage caused by hang-up to a minimum, by making the unit into modules by function units and by detecting the hang-up state and by making it possible to initialize the unit for every module.
CONSTITUTION: Though processor unit PU101 executes micro program FW stored in ROM103, other modules are hard-cleared simultaneously in the initialization routine of FW by writing all 1 to register REG110 for reset control, which is provided in device control unit DCU106, and writing all 0 to it next. Next, adapter FDC107 is instructed to read and load the part of FW, which is not stored in ROM103, from disc unit FDD to RAM104, and preset required for respective registers in each adapter is performed. After the initialization completion, the busy state of adapters such as FDC107 is monitored. The busy counter of PU101 is counted up from the busy state; and in case of overflow, the initializing signal is issused for the part causing over-flow.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54030779A JPS5839326B2 (en) | 1979-03-16 | 1979-03-16 | Initialization method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54030779A JPS5839326B2 (en) | 1979-03-16 | 1979-03-16 | Initialization method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55123715A true JPS55123715A (en) | 1980-09-24 |
| JPS5839326B2 JPS5839326B2 (en) | 1983-08-29 |
Family
ID=12313159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54030779A Expired JPS5839326B2 (en) | 1979-03-16 | 1979-03-16 | Initialization method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5839326B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS589488A (en) * | 1981-07-09 | 1983-01-19 | Pioneer Electronic Corp | Reset mechanism of central arithmetic processor of system having plural central arithmetic processors |
| JPS6174047A (en) * | 1984-09-18 | 1986-04-16 | Fujitsu Ltd | Channel reset processing system |
| JPS62127918A (en) * | 1985-11-28 | 1987-06-10 | Oki Electric Ind Co Ltd | Logic circuit |
| JPS63106027A (en) * | 1986-10-23 | 1988-05-11 | Sanyo Electric Co Ltd | Reset control circuit |
| JPH0187445U (en) * | 1987-11-28 | 1989-06-09 |
-
1979
- 1979-03-16 JP JP54030779A patent/JPS5839326B2/en not_active Expired
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS589488A (en) * | 1981-07-09 | 1983-01-19 | Pioneer Electronic Corp | Reset mechanism of central arithmetic processor of system having plural central arithmetic processors |
| JPS6174047A (en) * | 1984-09-18 | 1986-04-16 | Fujitsu Ltd | Channel reset processing system |
| JPS62127918A (en) * | 1985-11-28 | 1987-06-10 | Oki Electric Ind Co Ltd | Logic circuit |
| JPS63106027A (en) * | 1986-10-23 | 1988-05-11 | Sanyo Electric Co Ltd | Reset control circuit |
| JPH0187445U (en) * | 1987-11-28 | 1989-06-09 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5839326B2 (en) | 1983-08-29 |
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