JPS5524488A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS5524488A
JPS5524488A JP9790378A JP9790378A JPS5524488A JP S5524488 A JPS5524488 A JP S5524488A JP 9790378 A JP9790378 A JP 9790378A JP 9790378 A JP9790378 A JP 9790378A JP S5524488 A JPS5524488 A JP S5524488A
Authority
JP
Japan
Prior art keywords
range
grooves
type
substrate
openings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9790378A
Other languages
Japanese (ja)
Inventor
Kenjiro Yagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP9790378A priority Critical patent/JPS5524488A/en
Publication of JPS5524488A publication Critical patent/JPS5524488A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE: For increasing integration degree and operation speed and decreasing power consumption, to provide grooves in the surface of a semiconductor and to use said grooves for separation or to provide range for separation or draw-out for example by diffusing impurities on the wall faces of said grooves.
CONSTITUTION: N-type buried range 11 is diffusedly formed in a P-type Si substrate 1, N--layer 2 is epitaxially formed over the whole surface of said substrate 1, and said substrate 1 is covered with SiO2 film 71. Nixt, openings are provided in said film, one so as to correspond to an end portion of said range 11 and the other two so that said range 11 may be sandwiched therebetween, and V-shaped grooves 91W 93 extending up to said substrate 1 are provided by the etching in which said openings and isopropyl-alcoholic solution are used, the former as mask. Thereafter, said film 71 is renewed, openings are provided at a given range, and a plurality of P-type ranges 5 and P-type layer 3 for separation are diffusedly formed in said layer 2 sandwiched between said grooves 91 and 92 and on the wall faces of said grooves 91 and 93 respectively. Nixt, N-type range 6 and N-type draw-out range 4 are provided between said ranges 5 on the wall faces of said groove 92 respectively, and earthing electrode 81, injector 82, gate 83, drain 84 and draw-out electrode 85 for example are formed.
COPYRIGHT: (C)1980,JPO&Japio
JP9790378A 1978-08-11 1978-08-11 Semiconductor integrated circuit Pending JPS5524488A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9790378A JPS5524488A (en) 1978-08-11 1978-08-11 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9790378A JPS5524488A (en) 1978-08-11 1978-08-11 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5524488A true JPS5524488A (en) 1980-02-21

Family

ID=14204679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9790378A Pending JPS5524488A (en) 1978-08-11 1978-08-11 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5524488A (en)

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