JPS5575219A - Manufacturing semiconductor - Google Patents
Manufacturing semiconductorInfo
- Publication number
- JPS5575219A JPS5575219A JP14945278A JP14945278A JPS5575219A JP S5575219 A JPS5575219 A JP S5575219A JP 14945278 A JP14945278 A JP 14945278A JP 14945278 A JP14945278 A JP 14945278A JP S5575219 A JPS5575219 A JP S5575219A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- windows
- impurities
- source
- diffused
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE: To form source-drain regions and a channel by one high-temperature thermal treatment, by forming the first-solid layer containing impurities of a specified density on a semiconductor substrate and selectively removing the layer, thereafter forming the second-solid layer containing impurities whose density is different from the first-solid layer.
CONSTITUTION: An SiO2 film is deposited on a p-type Si substrate, and source- drain diffusing windows 2a and 2b are provided. A poly-crystal-Si-gate-electrode wiring 4 is formed on a remained SiO2 film 3. Then, a PSG layer 5 is deposited all over the surface by a gaseous-phase growth method. Etching is performed by a mixed gas of CF4 and O2 with a resist pattern as a mask, and portions 6 which are adjacent to the windows 2a and 2b are removed. Thereafter, a PSG layer 7 whose density is lower than that of the layer 5 is grown again all over the surface including the windows. The thermal treatment is made in an N2 gas of 1,000°C, and impurities in the layer 7 is diffused, thereby n-source-drain regions 8 and 9 are formed. At the same time, impurities are also diffused from the layers 5 and 7, and a channel is formed below the wiring 4.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14945278A JPS5575219A (en) | 1978-12-02 | 1978-12-02 | Manufacturing semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14945278A JPS5575219A (en) | 1978-12-02 | 1978-12-02 | Manufacturing semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5575219A true JPS5575219A (en) | 1980-06-06 |
Family
ID=15475421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14945278A Pending JPS5575219A (en) | 1978-12-02 | 1978-12-02 | Manufacturing semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5575219A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4499653A (en) * | 1983-11-03 | 1985-02-19 | Westinghouse Electric Corp. | Small dimension field effect transistor using phosphorous doped silicon glass reflow process |
| JPS6083372A (en) * | 1983-10-13 | 1985-05-11 | Fujitsu Ltd | Mis type semiconductor device and manufacture thereof |
| US5116784A (en) * | 1990-11-30 | 1992-05-26 | Tokyo Electron Limited | Method of forming semiconductor film |
| US5409843A (en) * | 1986-12-03 | 1995-04-25 | Fujitsu, Ltd. | Method of producing a semiconductor device by forming contacts after flowing a glass layer |
-
1978
- 1978-12-02 JP JP14945278A patent/JPS5575219A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6083372A (en) * | 1983-10-13 | 1985-05-11 | Fujitsu Ltd | Mis type semiconductor device and manufacture thereof |
| US4499653A (en) * | 1983-11-03 | 1985-02-19 | Westinghouse Electric Corp. | Small dimension field effect transistor using phosphorous doped silicon glass reflow process |
| US5409843A (en) * | 1986-12-03 | 1995-04-25 | Fujitsu, Ltd. | Method of producing a semiconductor device by forming contacts after flowing a glass layer |
| US5116784A (en) * | 1990-11-30 | 1992-05-26 | Tokyo Electron Limited | Method of forming semiconductor film |
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