JPS5646534A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5646534A
JPS5646534A JP12340479A JP12340479A JPS5646534A JP S5646534 A JPS5646534 A JP S5646534A JP 12340479 A JP12340479 A JP 12340479A JP 12340479 A JP12340479 A JP 12340479A JP S5646534 A JPS5646534 A JP S5646534A
Authority
JP
Japan
Prior art keywords
hole
semiconductor device
exposing
developing
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12340479A
Other languages
Japanese (ja)
Inventor
Yoshinori Teto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP12340479A priority Critical patent/JPS5646534A/en
Publication of JPS5646534A publication Critical patent/JPS5646534A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Landscapes

  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To readily inspect the etched film of a semiconductor device by employing a resist mask provided with a checking hole having the same width as a minimum window hole. CONSTITUTION:A testing hole 5a having the same width as a minimum window hole 3d is simultaneously formed at the outside of a diffused region 4 on the outer periphery of an IC2. After exposing and developing the photoresist, exposing and developing an etched insulating film or etching the insulating film, the opened degree of the hole 5a is confirmed and the opening degree of the window hole 3a having a prescribed minimum width can be evaluated according to this configuration. Since only the testing hole 5a is constantly confirmed in this manner, the checking work can become remarkably easy.
JP12340479A 1979-09-25 1979-09-25 Manufacture of semiconductor device Pending JPS5646534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12340479A JPS5646534A (en) 1979-09-25 1979-09-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12340479A JPS5646534A (en) 1979-09-25 1979-09-25 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5646534A true JPS5646534A (en) 1981-04-27

Family

ID=14859709

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12340479A Pending JPS5646534A (en) 1979-09-25 1979-09-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5646534A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02240236A (en) * 1989-03-15 1990-09-25 Nkk Corp Salt damage-resistant pc steel bar
US5805421A (en) * 1994-11-23 1998-09-08 Intel Corporation Semiconductor substrate having alignment marks for locating circuitry on the substrate
US5904486A (en) * 1997-09-30 1999-05-18 Intel Corporation Method for performing a circuit edit through the back side of an integrated circuit die
US5976980A (en) * 1994-11-23 1999-11-02 Intel Corporation Method and apparatus providing a mechanical probe structure in an integrated circuit die
US6020746A (en) * 1994-11-23 2000-02-01 Intel Corporation Method and apparatus for probing an integrated circuit through the back side of an integrated circuit die
US6153891A (en) * 1994-11-23 2000-11-28 Intel Corporation Method and apparatus providing a circuit edit structure through the back side of an integrated circuit die
US6159754A (en) * 1998-05-07 2000-12-12 Intel Corporation Method of making a circuit edit interconnect structure through the backside of an integrated circuit die
US6309897B1 (en) 1997-09-30 2001-10-30 Intel Corporation Method and apparatus providing a circuit edit structure through the back side of an integrated circuit die
US6692995B2 (en) 2002-04-05 2004-02-17 Intel Corporation Physically deposited layer to electrically connect circuit edit connection targets

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5397777A (en) * 1977-02-08 1978-08-26 Nec Corp Semiconductor device
JPS53127268A (en) * 1977-04-13 1978-11-07 Mitsubishi Electric Corp Size selection method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5397777A (en) * 1977-02-08 1978-08-26 Nec Corp Semiconductor device
JPS53127268A (en) * 1977-04-13 1978-11-07 Mitsubishi Electric Corp Size selection method

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02240236A (en) * 1989-03-15 1990-09-25 Nkk Corp Salt damage-resistant pc steel bar
US6122174A (en) * 1994-11-23 2000-09-19 Intel Corporation Method of accessing the circuitry on a semiconductor substrate from the bottom of the semiconductor substrate
US5952247A (en) * 1994-11-23 1999-09-14 Intel Corporation Method of accessing the circuitry on a semiconductor substrate from the bottom of the semiconductor substrate
US5976980A (en) * 1994-11-23 1999-11-02 Intel Corporation Method and apparatus providing a mechanical probe structure in an integrated circuit die
US6020746A (en) * 1994-11-23 2000-02-01 Intel Corporation Method and apparatus for probing an integrated circuit through the back side of an integrated circuit die
US5805421A (en) * 1994-11-23 1998-09-08 Intel Corporation Semiconductor substrate having alignment marks for locating circuitry on the substrate
US6153891A (en) * 1994-11-23 2000-11-28 Intel Corporation Method and apparatus providing a circuit edit structure through the back side of an integrated circuit die
US5904486A (en) * 1997-09-30 1999-05-18 Intel Corporation Method for performing a circuit edit through the back side of an integrated circuit die
US6150718A (en) * 1997-09-30 2000-11-21 Intel Corporation Method and apparatus for performing a circuit edit through the back side of an integrated circuit die
US6309897B1 (en) 1997-09-30 2001-10-30 Intel Corporation Method and apparatus providing a circuit edit structure through the back side of an integrated circuit die
US6159754A (en) * 1998-05-07 2000-12-12 Intel Corporation Method of making a circuit edit interconnect structure through the backside of an integrated circuit die
US6376919B1 (en) 1998-05-07 2002-04-23 Intel Corporation Circuit edit interconnect structure through the backside of an integrated circuit die
US6692995B2 (en) 2002-04-05 2004-02-17 Intel Corporation Physically deposited layer to electrically connect circuit edit connection targets
US7084497B2 (en) 2002-04-05 2006-08-01 Intel Corporation Physically deposited layer to electrically connect circuit edit connection targets

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