JPS5690538A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5690538A JPS5690538A JP16724579A JP16724579A JPS5690538A JP S5690538 A JPS5690538 A JP S5690538A JP 16724579 A JP16724579 A JP 16724579A JP 16724579 A JP16724579 A JP 16724579A JP S5690538 A JPS5690538 A JP S5690538A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- substrate
- region
- layer
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To avoid contact between first and second layer wirings by withdrawing the first layer wiring from the top thereof among those formed on an MOS transistor. CONSTITUTION:An N<+> type region is diffused into an N type Si substrate 1 to withdraw the substrate and P<+> type regions to serve as source and drain regions and entirely coated with a field insulator film. With a window opened, the first layer Al electrodes 3 are formed on the substrate withdrawing region and the source region and the first layer Al wiring on the drain region. Then, a gate electrode G is provided somewhere between the source and drain regions and entirely covered with a PSG inter lamilar insulator film 4. Thereafer, an opening is provided in the film 4 and the second layer Al wiring 5 is mounted on a wiring 3 connected to the drain region, a condition in which the wiring 3 provides on the substrate drawing region is withdrawn from the side of the substrate 1. This avoids contact between the wires 3 and 5, on withdrawn from the side and the other from the top thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16724579A JPS5690538A (en) | 1979-12-22 | 1979-12-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16724579A JPS5690538A (en) | 1979-12-22 | 1979-12-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5690538A true JPS5690538A (en) | 1981-07-22 |
Family
ID=15846144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16724579A Pending JPS5690538A (en) | 1979-12-22 | 1979-12-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5690538A (en) |
-
1979
- 1979-12-22 JP JP16724579A patent/JPS5690538A/en active Pending
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